Integrated circuit chip device

Abstract

An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

The invention claimed is: 
     
       1. An integrated circuit chip device, comprising:
 a main processing circuit; and 
 a plurality of basic processing circuits, 
 wherein:
 the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type; 
 the plurality of basic processing circuits are arranged as an array, each basic processing circuit is connected to an adjacent basic processing circuit, the main processing circuit is connected to n basic processing circuits in a first row, n basic processing circuits in an m th  row, and m basic processing circuits in a first column; 
 the main processing circuit is configured to:
 obtain an input data block, a convolution kernel data block, and a convolution instruction; 
 convert the input data block and the convolution kernel data block to an input data block of the fixed point type and a convolution kernel data block of the fixed point type, respectively, using the data type conversion circuit; 
 classify the input data block of the fixed point type into a broadcasting data block of the fixed point type according to the convolution instruction; 
 classify the convolution kernel data block of the fixed point type into a distribution data block of the fixed point type according to the convolution instruction; 
 partition the distribution data block of the fixed point type to obtain a plurality of basic data blocks of the fixed point type; 
 distribute the plurality of basic data blocks of the fixed point type to at least one of the plurality of basic processing circuits connected to the main processing circuit; and 
 broadcast the broadcasting data block of the fixed point type to one or more basic processing circuits connected to the main processing circuit; 
 
 at least one of the plurality of basic processing circuits is configured to:
 perform computations of a neural network in parallel with at least another one of the plurality of basic processing circuits according to the broadcasting data block of the fixed point type and the basic data blocks of the fixed point type to obtain computation results; and 
 transfer the computation results to the main processing circuit; and 
 
 the main processing circuit is further configured to:
 process the computation results to obtain an instruction result of the convolution instruction. 
 
 
 
     
     
       2. The integrated circuit chip device of  claim 1 , wherein:
 the at least one of the plurality of basic processing circuits is configured to:
 perform inner product computations on the broadcasting data block of the fixed point type and the received basic data blocks of the fixed point type to obtain inner products of the fixed point type; 
 accumulate the inner products of the fixed point type to obtain accumulation results of the fixed point type; and 
 transfer the accumulation results of the fixed point type as the computation results of the fixed point type to the main processing circuit; and 
 
 the main processing circuit is configured to:
 convert the computation results of the fixed point type to computation results of the floating point type using the data type conversion circuit; and 
 sort the computation results of the floating point type to obtain the instruction result. 
 
 
     
     
       3. The integrated circuit chip device of  claim 1 , wherein:
 the at least one of the plurality of basic processing circuits is configured to:
 perform inner product computations on the broadcasting data block of the fixed point type and the received basic data blocks of the fixed point type to obtain inner products of the fixed point type; and 
 transfer the inner products of the fixed point type as the computation results to the main processing circuit through the basic processing circuits that are connected to the main processing circuit; and 
 
 the main processing circuit is configured to:
 convert the inner products of the fixed point type to inner products of the floating point type using the data type conversion circuit; 
 accumulate the inner products of the floating point type to obtain accumulation results; and 
 sort the accumulation results to obtain the instruction result. 
 
 
     
     
       4. The integrated circuit chip device of  claim 1 , wherein:
 the main processing circuit is configured to:
 broadcast the broadcasting data block of the fixed point type as a whole to the basic processing circuits that are connected to the main processing circuit. 
 
 
     
     
       5. The integrated circuit chip device of  claim 1 , wherein:
 the main processing circuit is configured to:
 partition the broadcasting data block of the fixed point type into a plurality of partial broadcasting data blocks; and 
 sequentially broadcast the plurality of partial broadcasting data blocks to the basic processing circuits that are connected to the main processing circuit. 
 
 
     
     
       6. The integrated circuit chip device of  claim 5 , wherein:
 the at least one of the plurality of basic processing circuits is configured to:
 perform inner product processing on the partial broadcasting data blocks and the basic data blocks of the fixed point type to obtain results of inner product processing; 
 accumulate the results of inner product processing to obtain partial computation results; and 
 transfer the partial computation results to the main processing circuit. 
 
 
     
     
       7. The integrated circuit chip device of  claim 5 , wherein:
 the at least one of the plurality of basic processing circuits is configured to:
 reuse the partial broadcasting data blocks for p times; 
 perform p times of inner product computations on the partial broadcasting data blocks and p basic data blocks of the fixed point type to obtain p groups of inner product computation results, wherein the p groups of inner product computation results correspond to the p basic data blocks; 
 accumulate inner product computation results in each of the p groups of inner product computation results to obtain p partial computation results; and 
 transfer the p partial computation results to the main processing circuit, wherein p is an integer greater than or equal to 2. 
 
 
     
     
       8. The integrated circuit chip device of  claim 1 , wherein:
 the main processing circuit includes a main register or a main on-chip caching circuit; 
 each basic processing circuit includes a basic register or a basic on-chip caching circuit. 
 
     
     
       9. The integrated circuit chip device of  claim 1 , wherein:
 the main processing circuit includes at least one of:
 a vector computing unit circuit, an arithmetic and logic unit circuit, an accumulator circuit, a matrix transposition circuit, a direct memory access circuit, or a data rearrangement circuit. 
 
 
     
     
       10. The integrated circuit chip device of  claim 1 , wherein:
 the input data block includes at least one of a matrix, a three-dimensional data block, a four-dimensional data block, and an n-dimensional data block; and 
 the convolution kernel data block includes at least one of a matrix, a three-dimensional data block, a four-dimensional data block, and an n-dimensional data block. 
 
     
     
       11. A processing device, comprising:
 a general processing device; 
 a general interconnection interface; and 
 a neural network computing device connected to the general processing device through the general interconnection interface, wherein the neural network computing device comprises:
 a main processing circuit; and 
 a plurality of basic processing circuits, 
 wherein:
 the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type; 
 the plurality of basic processing circuits are arranged as an array, each basic processing circuit is connected to an adjacent basic processing circuit, the main processing circuit is connected to n basic processing circuits in a first row, n basic processing circuits in an m th  row, and m basic processing circuits in a first column; 
 the main processing circuit is configured to:
 obtain an input data block, a convolution kernel data block, and a convolution instruction; 
 convert the input data block and the convolution kernel data block to an input data block of the fixed point type and a convolution kernel data block of the fixed point type, respectively, using the data type conversion circuit; 
 classify the input data block of the fixed point type into a broadcasting data block of the fixed point type according to the convolution instruction; 
 classify the convolution kernel data block of the fixed point type into a distribution data block of the fixed point type according to the convolution instruction; 
 partition the distribution data block of the fixed point type to obtain a plurality of basic data blocks of the fixed point type; 
 distribute the plurality of basic data blocks of the fixed point type to at least one of the plurality of basic processing circuits connected to the main processing circuit; and 
 broadcast the broadcasting data block of the fixed point type to one or more basic processing circuits connected to the main processing circuit; 
 
 at least one of the plurality of basic processing circuits is configured to:
 perform computations of a neural network in parallel with at least another one of the plurality of basic processing circuits according to the broadcasting data block of the fixed point type and the basic data blocks of the fixed point type to obtain computation results; and 
 transfer the computation results to the main processing circuit; and 
 
 the main processing circuit is further configured to:
 process the computation results to obtain an instruction result of the convolution instruction. 
 
 
 
 
     
     
       12. A method, implemented by an integrated circuit chip device comprising a main processing circuit and a plurality of basic processing circuits, for performing neural network operations, the method comprising:
 obtaining, by the main processing circuit, an input data block, a convolution kernel data block, and a convolution instruction; 
 converting, by a data type conversion circuit of the main processing circuit, the input data block and the convolution kernel data block to an input data block of the fixed point type and a convolution kernel data block of the fixed point type, respectively; 
 classifying, by the main processing circuit, the input data block of the fixed point type into a broadcasting data block of the fixed point type according to the convolution instruction; 
 classifying, by the main processing circuit, the convolution kernel data block of the fixed point type into a distribution data block of the fixed point type according to the convolution instruction; 
 partitioning, by the main processing circuit, the distribution data block of the fixed point type to obtain a plurality of basic data blocks of the fixed point type; 
 distributing, by the main processing circuit, the plurality of basic data blocks of the fixed point type to at least one of the plurality of basic processing circuits connected to the main processing circuit; 
 broadcasting, by the main processing circuit, the broadcasting data block of the fixed point type to one or more basic processing circuits connected to the main processing circuit; 
 performing, by the at least one of the plurality of basic processing circuits, computations of a neural network in parallel with at least another one of the plurality of basic processing circuits according to the broadcasting data block of the fixed point type and the basic data blocks of the fixed point type to obtain computation results; 
 transferring, by the at least one of the plurality of basic processing circuits, the computation results to the main processing circuit; and 
 processing, by the main processing circuit, the computation results to obtain an instruction result of the convolution instruction. 
 
     
     
       13. The method of  claim 12 , further comprising:
 performing, by the at least one of the plurality of basic processing circuits, inner product computations on the broadcasting data block of the fixed point type and the received basic data blocks of the fixed point type to obtain inner products of the fixed point type; 
 accumulating, by the at least one of the plurality of basic processing circuits, the inner products of the fixed point type to obtain accumulation results of the fixed point type; 
 transferring, by the at least one of the plurality of basic processing circuits, the accumulation results of the fixed point type as the computation results of the fixed point type to the main processing circuit; 
 converting, by the main processing circuit, the computation results of the fixed point type to computation results of the floating point type using the data type conversion circuit; and 
 sorting, by the main processing circuit, the computation results of the floating point type to obtain the instruction result. 
 
     
     
       14. The method of  claim 12 , further comprising:
 performing, by the at least one of the plurality of basic processing circuits, inner product computations on the broadcasting data block of the fixed point type and the received basic data blocks of the fixed point type to obtain inner products of the fixed point type; 
 transferring, by the at least one of the plurality of basic processing circuits, the inner products of the fixed point type as the computation results to the main processing circuit through the basic processing circuits that are connected to the main processing circuit; 
 converting, by the main processing circuit, the inner products of the fixed point type to inner products of the floating point type using the data type conversion circuit; 
 accumulating, by the main processing circuit, the inner products of the floating point type to obtain accumulation results; and 
 sorting, by the main processing circuit, the accumulation results to obtain the instruction result. 
 
     
     
       15. The method of  claim 12 , further comprising:
 broadcasting, by the main processing circuit, the broadcasting data block of the fixed point type as a whole to the basic processing circuits that are connected to the main processing circuit. 
 
     
     
       16. The method of  claim 12 , further comprising:
 partitioning, by the main processing circuit, the broadcasting data block of the fixed point type into a plurality of partial broadcasting data blocks; and 
 sequentially broadcasting, by the main processing circuit, the plurality of partial broadcasting data blocks to the basic processing circuits that are connected to the main processing circuit. 
 
     
     
       17. The method of  claim 16 , further comprising:
 performing, by the at least one of the plurality of basic processing circuits, inner product processing on the partial broadcasting data blocks and the basic data blocks of the fixed point type to obtain results of inner product processing; 
 accumulating, by the at least one of the plurality of basic processing circuits, the results of inner product processing to obtain partial computation results; and 
 transferring, by the at least one of the plurality of basic processing circuits, the partial computation results to the main processing circuit. 
 
     
     
       18. The method of  claim 16 , further comprising:
 reusing, by the at least one of the plurality of basic processing circuits, the partial broadcasting data blocks for p times; 
 performing, by the at least one of the plurality of basic processing circuits, p times of inner product computations on the partial broadcasting data blocks and p basic data blocks of the fixed point type to obtain p groups of inner product computation results, wherein the p groups of inner product computation results correspond to the p basic data blocks; 
 accumulating, by the at least one of the plurality of basic processing circuits, inner product computation results in each of the p groups of inner product computation results to obtain p partial computation results; and 
 transferring, by the at least one of the plurality of basic processing circuits, the p partial computation results to the main processing circuit, wherein p is an integer greater than or equal to 2. 
 
     
     
       19. The method of  claim 12 , wherein:
 the main processing circuit includes a main register or a main on-chip caching circuit; and 
 each basic processing circuit includes a basic register or a basic on-chip caching circuit. 
 
     
     
       20. The method of  claim 12 , wherein:
 the main processing circuit includes at least one of:
 a vector computing unit circuit, an arithmetic and logic unit circuit, an accumulator circuit, a matrix transposition circuit, a direct memory access circuit, or a data rearrangement circuit.