Array substrate and display panel

Abstract

An array substrate and a display panel are disclosed in an embodiment of the present application. The array substrate includes a plurality of GOA units in cascade and a plurality of clock signal lines. The plurality of clock signal lines are arranged on one side of the GOA units and are arranged at intervals along a direction away from the GOA units. The plurality of GOA units are electrically connected to the plurality of clock signal lines, respectively. Wherein, a number of the GOA units electrically connected to each of the clock signal lines is equal. The array substrate reduces a resistance difference and a capacitance difference between the plurality of clock signal lines and alleviates a problem of dense horizontal lines by adjusting a number of stages of the GOA units.

What is claimed is: 
     
       1. An array substrate, comprising:
 a plurality of gate driver on array (GOA) units in cascade; and 
 a plurality of clock signal lines arranged on one side of the GOA units and arranged at intervals along a direction away from the GOA units, and the plurality of GOA units electrically connected to the plurality of clock signal lines, respectively; wherein a number of the GOA units electrically connected to each of the clock signal lines is equal, 
 wherein at least one of the clock signal lines comprises a clock signal main line and a clock signal branch line corresponding to the clock signal main line; one end of the clock signal branch line is electrically connected to the corresponding clock signal main line, and another end of the clock signal branch line is electrically connected to a corresponding GOA unit, 
 wherein at least one of the clock signal lines further comprises a compensation branch line; one end of the compensation branch line is electrically connected to the corresponding clock signal branch line, and another end of the compensation branch line is electrically connected to the corresponding GOA unit, 
 wherein a sum of lengths of the plurality of clock signal branch lines is equal to a sum of lengths of the compensation branch lines. 
 
     
     
       2. The array substrate as claimed in  claim 1 , wherein the GOA units are electrically connected to at least one of the clock signal lines, and a number of the GOA units is N times of a number of the clock signal lines, and N is an integer greater than or equal to 1. 
     
     
       3. The array substrate as claimed in  claim 2 , wherein the plurality of GOA units comprise a plurality of virtual GOA units, a number of the virtual GOA units is equal to the number of the clock signal lines, and the virtual GOA units are connected to the clock signal lines in a one-to-one correspondence. 
     
     
       4. The array substrate as claimed in  claim 3 , wherein the compensation branch line comprises a first connecting section electrically connected to the corresponding clock signal branch line, a bending-connecting section, and a second connecting section electrically connected to the corresponding virtual GOA unit; and the bending-connecting section is arranged between the first connecting section and the second connecting sections. 
     
     
       5. The array substrate as claimed in  claim 1 , wherein a winding area is provided between the GOA units and the clock signal lines, and the compensation branch line is arranged in the winding area. 
     
     
       6. The array substrate as claimed in  claim 1 , wherein the array substrate further comprises a plurality of capacitance compensation blocks, the plurality of capacitance compensation blocks are electrically connected to the plurality of clock signal lines and are used to compensate capacitance generated in an area directly opposite to the plurality of clock signal branch lines and lines in the GOA units, and/or capacitance generated in an area directly opposite to the plurality of clock signal branch lines and the clock signal main lines. 
     
     
       7. The array substrate as claim in  claim 6 , wherein a cross-sectional area of the capacitance compensation block is negatively correlated with the distance between the clock signal main line and the virtual GOA unit. 
     
     
       8. A display panel, comprising the array substrate as claimed in  claim 1 .