Dynamic random-access memory (DRAM) training acceleration

Abstract

A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

What is claimed is: 
     
       1. A method for performing read training of a memory channel comprising:
 writing a data pattern to a memory using a data bus having a predetermined number of bit lanes; and 
 determining an edge of a read data eye individually for each bit lane by: 
 reading said data pattern over said data bus using a read burst cycle having a predetermined length; 
 grouping data received on each bit lane over said read burst cycle to form a corresponding bit lane data group; 
 comparing said corresponding bit lane data group to expected data for each bit lane; 
 logging a phase of each bit lane on which said edge is found; and 
 repeating said reading, grouping, comparing, and logging until said edge is found for all of said bit lanes. 
 
     
     
       2. The method of  claim 1 , further comprises starting said determining at an approximate center of said read data eye. 
     
     
       3. The method of  claim 2 , further comprising:
 determining said approximate center by reading data from said predetermined number of bit lanes together. 
 
     
     
       4. The method of  claim 2 , further comprising:
 generating said data pattern as a pseudo-random number using a linear feedback shift register. 
 
     
     
       5. The method of  claim 2 , wherein said determining said edge of said read data eye individually for each bit lane comprises:
 determining a right edge of said read data eye for a first plurality of different delays from said approximate center to successively larger delays until said right edge of said read data eye is found; and 
 determining a left edge of said read data eye for a second plurality of different delays from said approximate center to successively smaller delays until said left edge of said read data eye is found. 
 
     
     
       6. The method of  claim 5 , further comprising:
 setting a phase of a read delay for each bit lane to a center position of a corresponding right edge and a corresponding left edge for each bit lane. 
 
     
     
       7. The method of  claim 6 , further comprising:
 performing write data eye training by writing data at various delays and reading data at said phase of said read delay for each bit lane. 
 
     
     
       8. A method for performing read training of a memory channel comprising:
 programming a memory with a data pattern using a burst write cycle having a predetermined length over a data bus having a predetermined number of bit lanes; 
 searching for a right edge of a read data eye for each bit lane by comparing received data bits transmitted on a corresponding bit lane for each beat of a corresponding burst read cycle having said predetermined length with corresponding expected data from said data pattern; 
 searching for a left edge of said read data eye for each bit lane by comparing received data bits transmitted on said corresponding bit lane for each beat of a corresponding burst read cycle with said corresponding expected data from said data pattern; and 
 setting a corresponding read delay for each bit lane independently based on corresponding left and right edges of said read data eye. 
 
     
     
       9. The method of  claim 8 , further comprising:
 generating said corresponding expected data comprises by de-multiplexing said data pattern based on a number of bit lanes in the memory channel. 
 
     
     
       10. The method of  claim 8 , further comprising:
 determining an approximate center by reading data from said predetermined number of bit lanes together. 
 
     
     
       11. The method of  claim 10 , wherein said searching for said right edge of said read data eye for each bit lane comprises:
 setting a delay for each bit lane to said approximate center; 
 incrementing said delay for each bit lane by a predetermined amount; 
 reading data using a burst read cycle having said predetermined length; 
 grouping data of said read burst cycle per bit lane; 
 comparing each group of data to said corresponding expected data from said data pattern; 
 logging a current phase into a bit lane right edge register if said comparing indicates a first failing value to said corresponding bit lane; and 
 repeating said incrementing, said reading data, said grouping data, said comparing, and said logging until all bit lane groups fail. 
 
     
     
       12. The method of  claim 10 , wherein said searching for said left edge of said read data eye for each bit lane comprises:
 setting a delay for each bit lane to said approximate center; 
 decrementing said delay for each bit lane by a predetermined amount; 
 reading data using a burst read cycle having said predetermined length; 
 grouping data of said read burst cycle per bit lane; 
 comparing each group of data to said corresponding expected data from said data pattern; 
 logging a current phase into a bit lane right edge register if said comparing indicates a first failing value to said corresponding bit lane; and 
 repeating said decrementing, said reading data, said grouping data, said comparing, and said logging until all bit lane groups fail. 
 
     
     
       13. The method of  claim 8 , further comprising:
 setting a phase of a read delay for each bit lane to a center position of a corresponding right edge and a corresponding left edge for each bit lane. 
 
     
     
       14. The method of  claim 13 , further comprising:
 performing write data eye training by writing data at various delays and reading data at a respective center position for each bit lane. 
 
     
     
       15. A memory controller, comprising:
 a training engine for writing a data pattern to a memory using a data bus having a predetermined number of bit lanes; and 
 a built-in self-test circuit coupled to said training engine, comprising:
 a selection circuit having an input for receiving said data pattern for forming a plurality of bit lane data groups of expected data for each bit lane wherein each bit lane data group comprises a predetermined number of bits received on a corresponding bit lane during a read cycle; and 
 a data comparison circuit for comparing bits in each bit lane data group to corresponding received data, and having an output for providing a corresponding match signal for each data lane. 
 
 
     
     
       16. The memory controller of  claim 15 , wherein said built-in self-test circuit further comprises:
 a linear feedback shift register for generating said data pattern. 
 
     
     
       17. The memory controller of  claim 15 , wherein said built-in self-test circuit further comprises:
 a data bus inversion generation circuit responsive to said data pattern for generating a data bus inversion (DBI) code according to said data pattern and a predetermined DBI algorithm; and 
 a data bus inversion comparison circuit for comparing bits of said DBI code to received DBI signals, and having an output for providing a match signal for each DBI signal. 
 
     
     
       18. The memory controller of  claim 17 , wherein said predetermined DBI algorithm comprises:
 a DBI DC  pattern. 
 
     
     
       19. The memory controller of  claim 17 , wherein said predetermined DBI algorithm comprises:
 a DBI AC  pattern. 
 
     
     
       20. The memory controller of  claim 17 , further comprising:
 a status register coupled to said training engine, having a plurality of fields for storing match signals for corresponding bit lanes.