Floating gate memristor device and neuromorphic device having the same

Abstract

Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

What is claimed is: 
     
       1. A floating gate memristor device comprising:
 a substrate; 
 a floating gate disposed on the substrate; 
 an insulating layer covering the floating gate; 
 a semiconductor channel disposed on the insulating layer and vertically overlapping the floating gate; 
 a first electrode including a plurality of control terminals disposed on the semiconductor channel and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; and 
 a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode. 
 
     
     
       2. The floating gate memristor device of  claim 1 , wherein the second electrode is disposed on the semiconductor channel. 
     
     
       3. The floating gate memristor device of  claim 1 , wherein the second electrode is disposed between the substrate and the floating gate and vertically overlaps all of the control terminals. 
     
     
       4. The floating gate memristor device of  claim 1 , wherein a control voltage selected from a group consisting of a ground voltage, a first control voltage greater than the ground voltage, and a second control voltage lower than the ground voltage is sequentially applied to the control terminals at a predetermined interval,
 wherein when a control voltage is applied to a first control terminal of the control terminals, charges tunnel between the first control terminal and the floating gate, 
 wherein an amount of current flowing through the semiconductor channel or a conductance of the semiconductor channel is controlled based on the control voltages applied to the control terminals.