Semiconductor device

Abstract

A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor layer having a first main surface on one side and a second main surface on the other side; 
 a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface, a well region of a second conductivity type formed in the surface layer portion of the first main surface along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region; 
 a gate electrode layer that faces the well region and the first conductivity type region across a gate insulating layer, and that has a side wall located on the first conductivity type region; 
 an insulating film that covers over the gate electrode layer; and 
 a first main surface electrode electrically connected to the diode region and the first conductivity type region on the first main surface, the first main surface electrode forming a Schottky junction with the diode region, 
 wherein the first main surface of the semiconductor layer includes a recessed portion that is formed in a region located at a side of the gate electrode layer such as to be recessed toward the second main surface and that exposes at least a part of the first conductivity type region, 
 the insulating film has a first portion that covers the recessed portion and extends along the recessed portion from the side wall of the gate electrode layer and a second portion that covers the side wall of the gate electrode layer and extends along the side wall of the gate electrode layer, and 
 a thickness of the first portion of the insulating film perpendicular to an extending direction of the first portion of the insulating film is greater than a thickness of the second portion of the insulating film perpendicular to an extending direction of the second portion of the insulating film. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the well region forms a p-n junction portion with the diode region, and
 the unit cell has a junction barrier Schottky (JBS) structure including the p-n junction portion formed between the well region and the diode region. 
 
     
     
       3. The semiconductor device according to  claim 1 , wherein the well region surrounds the diode region in plan view. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the unit cell includes a contact region of the second conductivity type formed in a region between the diode region and the first conductivity type region in the surface layer portion of the well region and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the well region, and
 the recessed portion exposes at least a part of the contact region together with at least the part of the first conductivity type region. 
 
     
     
       5. The semiconductor device according to  claim 4 , wherein the contact region forms a p-n junction portion with the diode region, and
 the unit cell has a junction barrier Schottky (JBS) structure including the p-n junction portion formed between the contact region and the diode region. 
 
     
     
       6. The semiconductor device according to  claim 1 , wherein a plurality of the unit cells are formed in the surface layer portion of the first main surface, and
 the gate electrode layer faces a portion of the well region of each the unit cell. 
 
     
     
       7. The semiconductor device according to  claim 6 , wherein the plurality of unit cells are arrayed in at least one of a matrix pattern or a staggered pattern at intervals in an arbitrary first direction and a second direction intersecting the first direction. 
     
     
       8. The semiconductor device according to  claim 1 , wherein the unit cell is formed as a linear cell extending in an arbitrary one direction. 
     
     
       9. The semiconductor device according to  claim 1 , wherein the semiconductor layer includes a semiconductor substrate that forms the second main surface and an epitaxial layer that is formed on the semiconductor substrate and forms the first main surface. 
     
     
       10. The semiconductor device according to  claim 1 , further comprising a second main surface electrode which covers the second main surface of the semiconductor layer. 
     
     
       11. A semiconductor device comprising:
 a semiconductor layer having a first main surface on one side and a second main surface on the other side; 
 a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface, a well region of a second conductivity type formed in the surface layer portion of the first main surface along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region; 
 a gate electrode layer that faces the well region and the first conductivity type region across a gate insulating layer, and that has a side wall located on the first conductivity type region; 
 an insulating layer that covers over the gate electrode layer; and 
 a first main surface electrode electrically connected to the diode region and the first conductivity type region on the first main surface, the first main surface electrode forming a Schottky junction with the diode region, 
 wherein the first main surface of the semiconductor layer includes a recessed portion that is formed in a region located at a side of the gate electrode layer such as to be recessed toward the second main surface and that exposes at least a part of the first conductivity type region, 
 the insulating layer has a first portion that covers the recessed portion and extends along the recessed portion from the side wall of the gate electrode layer and a second portion that covers the side wall of the gate electrode layer and extends along the side wall of the gate electrode layer, and 
 a thickness of the first portion of the insulating layer along a normal direction of the first main surface is greater than a thickness of the gate insulating layer along the normal direction. 
 
     
     
       12. The semiconductor device according to  claim 11 , wherein the well region forms a p-n junction portion with the diode region, and
 the unit cell has a junction barrier Schottky (JBS) structure including the p-n junction portion formed between the well region and the diode region. 
 
     
     
       13. The semiconductor device according to  claim 11 , wherein the well region surrounds the diode region in plan view. 
     
     
       14. The semiconductor device according to  claim 11 , wherein the unit cell includes a contact region of the second conductivity type formed in a region between the diode region and the first conductivity type region in the surface layer portion of the well region and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the well region, and
 the recessed portion exposes at least a part of the contact region together with at least the part of the first conductivity type region. 
 
     
     
       15. The semiconductor device according to  claim 14 , wherein the contact region forms a p-n junction portion with the diode region, and
 the unit cell has a junction barrier Schottky (JBS) structure including the p-n junction portion formed between the contact region and the diode region. 
 
     
     
       16. The semiconductor device according to  claim 11 , wherein a plurality of the unit cells are formed in the surface layer portion of the first main surface, and
 the gate electrode layer faces a portion of the well region of each the unit cell. 
 
     
     
       17. The semiconductor device according to  claim 16 , wherein the plurality of unit cells are arrayed in at least one of a matrix pattern or a staggered pattern at intervals in an arbitrary first direction and a second direction intersecting the first direction. 
     
     
       18. The semiconductor device according to  claim 11 , wherein the unit cell is formed as a linear cell extending in an arbitrary one direction. 
     
     
       19. The semiconductor device according to  claim 11 , wherein the semiconductor layer includes a semiconductor substrate that forms the second main surface and an epitaxial layer that is formed on the semiconductor substrate and that forms the first main surface. 
     
     
       20. The semiconductor device according to  claim 11 , further comprising a second main surface electrode which covers the second main surface of the semiconductor layer and forms an ohmic junction with the semiconductor layer.