Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses

Abstract

Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.

What is claimed is: 
     
       1. An apparatus, comprising:
 a master die; 
 a target die including data storage elements; 
 inter-die data connectors electrically coupling the master die to the target die, the inter-die data connectors configured to conduct write data bits from the master die to the target die, the write data bits to be written to the data storage elements; and 
 inter-die error correction connectors electrically coupling the master die to the target die, the inter-die error correction connectors separate from the inter-die data connectors, the inter-die error correction connectors configured to conduct error correction information corresponding to the write data bits from the master die to the target die, 
 wherein the target die comprises error correction circuitry configured to: 
 generate new error correction information responsive to the write data bits received from the master die. 
 
     
     
       2. The apparatus of  claim 1 , wherein at least a portion of the inter-die data connectors and the inter-die error correction connectors comprises through-silicon-vias (TSVs). 
     
     
       3. The apparatus of  claim 1 , wherein at least a portion of the inter-die data connectors and the inter-die error correction connectors comprises wire bonds. 
     
     
       4. The apparatus of  claim 1 , wherein the inter-die error correction connectors comprise two of the inter-die error correction connectors for every eight of the inter-die data connectors. 
     
     
       5. The apparatus of  claim 1 , wherein the error correction information comprises cyclic redundancy check (CRC) bits. 
     
     
       6. The apparatus of  claim 1 , wherein the error correction information comprises two error correction bits for every sixteen of the write data bits. 
     
     
       7. The apparatus of  claim 1 , wherein the error correction circuitry is configured to provide error information to the master die responsive to the new error correction information not matching the error correction information received from the master die. 
     
     
       8. The apparatus of  claim 1 , further comprising control circuitry operably coupled to the master die, the control circuitry configured to receive error information from the master die and repeat a write operation responsive to the error information. 
     
     
       9. The apparatus of  claim 1 , wherein the error correction circuitry of the target die is further configured to:
 receive read data from the data storage elements; 
 generate error correction information corresponding to the read data; and 
 provide the error correction information to be transmitted to the master die. 
 
     
     
       10. The apparatus of  claim 1 , wherein:
 the inter-die data connectors are also configured to conduct read data bits read from the data storage elements from the target die to the master die; and 
 the inter-die error correction connectors are configured to conduct read error correction information determined responsive at least to the read data bits by the target die from the target die to the master die. 
 
     
     
       11. The apparatus of  claim 1 , wherein the master die includes clock circuitry configured to clock target data shift registers of the target die to shift the write data bits from the master die to the target die via the inter-die data connectors in two bursts of eight bits each for every nine clock cycles of a clock provided to the clock circuitry. 
     
     
       12. The apparatus of  claim 11 , wherein the clock circuitry is further configured to clock target error shift registers of the target die to shift the error correction information from the master die to the target die via the inter-die error correction connectors in a single burst of two bits for every nine clock cycles of the clock. 
     
     
       13. A computing system comprising a memory device, the memory device comprising:
 a stack of memory dies including: 
 a plurality of target dies, each of the plurality of target dies including data storage elements; 
 control circuitry including write error correction circuitry configured to generate error correction information corresponding to write data bits to be written to the data storage elements of one of the plurality of target dies; 
 a master die configured to serve as an interface between the control circuitry and each of the plurality of target dies; 
 inter-die data connectors operably coupling the master die to each of the plurality of target dies, the inter-die data connectors configured to conduct the write data bits from the master die to the plurality of target dies; and 
 inter-die error correction connectors separate from the inter-die data connectors, the inter-die error correction connectors operably coupling the master die to each of the plurality of target dies, the inter-die error correction connectors configured to conduct the error correction information corresponding to the write data bits from the master die to the plurality of target dies. 
 
     
     
       14. The computing system of  claim 13 , further comprising:
 one or more processors operably coupled to the memory device; 
 one or more non-volatile data storage devices operably coupled to the one or more processors; 
 one or more input devices operably coupled to the one or more processors; and 
 one or more output devices operably coupled to the one or more processors. 
 
     
     
       15. The computing system of  claim 13 , wherein the inter-die error correction connectors include two of the inter-die error correction connectors for every eight of the inter-die data connectors. 
     
     
       16. The computing system of  claim 13 , wherein each of the plurality of target dies further includes read error correction circuitry configured to generate error correction information corresponding to read data bits read from the data storage elements. 
     
     
       17. The computing system of  claim 16 , wherein the inter-die error correction connectors are further configured to conduct the error correction information corresponding to the read data bits from the plurality of target dies to the master die. 
     
     
       18. The computing system of  claim 16 , wherein the inter-die data connectors are further configured to conduct the read data bits from the plurality of target dies to the master die. 
     
     
       19. A method of operating a stack of memory dies, the method comprising:
 receiving, by a master die of the stack of memory dies, write data bits and error correction information associated with the write data bits from control circuitry; 
 conducting the write data bits to a target die of the stack of memory dies through inter-die data connectors; 
 conducting the error correction information associated with the write data bits to the target die through inter-die error correction connectors; 
 generating, by the target die, new error correction information associated with the write data bits received by the target die from the master die; and 
 comparing, by the target die, the error correction information received from the master die to the new error correction information. 
 
     
     
       20. The method of  claim 19 , further comprising:
 generating error information responsive to a determination that the error correction information received from the master die is different from the new error correction information; and 
 writing the write data bits to data storage elements of the target die responsive to a determination that the error correction information received from the master die matches the new error correction information.