Storage controller, storage device, and operation method of storage device

Abstract

An operation method of a storage device, which includes a storage controller and a nonvolatile memory device, includes performing first boot-up operation, performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals, storing offset information generated based on a result of the first training, performing a normal operation based on the result of the first training, performing a second boot-up operation, performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals, and performing the normal operation based on a result of the second training.

What is claimed is: 
     
       1. An operation method of a storage device which includes a storage controller circuit and a nonvolatile memory device, the method comprising:
 performing a first boot-up operation; 
 performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals; 
 storing offset information generated based on a result of the first training; 
 performing a normal operation based on the result of the first training; 
 performing a second boot-up operation; 
 performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of the windows of the data signals; and 
 performing the normal operation based on a result of the second training, 
 wherein the detection operation of the first training includes:
 sending, by the storage controller circuit, a read command and an address to the nonvolatile memory device through the plurality of data signals; 
 receiving, by the storage controller circuit, pattern data from the nonvolatile memory device through the plurality of data signals and a data strobe signal synchronized with the plurality of data signals; and 
 when the pattern data are not matched with given reference data, adjusting, by the storage controller circuit, a delay amount of the data strobe signal. 
 
 
     
     
       2. The method of  claim 1 , further comprising:
 loading the offset information before the second training is performed. 
 
     
     
       3. The method of  claim 1 , further comprising:
 updating the offset information based on the result of the second training after the second training is performed. 
 
     
     
       4. The method of  claim 1 , wherein the performing of the second training on the plurality of data signals comprises:
 Repeatedly performing, by the storage controller circuit, the detection operation of the second training to detect a left edge (LE) of each of the plurality of data signals; 
 Repeatedly performing, by the storage controller circuit, the detection operation of the second training to detect a right edge (RE) of each of the plurality of data signals; and 
 detecting a window of a data signal based on the LE and the RE. 
 
     
     
       5. The method of  claim 4 , wherein the repeatedly performing the detection operation of the second training to detect the LE by the storage controller circuit comprises:
 setting a left edge section based on LE offsets of the offset information; 
 performing the detection operation on the left edge section; and 
 when the pattern data are matched with the given reference data, setting a final LE offset. 
 
     
     
       6. The method of  claim 1 , wherein the offset information includes a left edge (LE) offset and a right edge (RE) offset associated with each of the plurality of data signals. 
     
     
       7. The method of  claim 1 , further comprising:
 aligning, by the storage controller circuit, the data signals and the data strobe signal based on the offset information. 
 
     
     
       8. A storage device comprising:
 a nonvolatile memory device; and 
 a storage controller circuit connected with the nonvolatile memory device through a plurality of data signals, 
 wherein, the storage controller circuit is configured such that, based on performing a first boot-up operation, the storage controller circuit performs first training on the plurality of data signals and generates offset information based on a result of the first training, 
 wherein, the storage controller circuit is further configured such that, based on performing a second boot-up operation, the storage controller circuit performs second training on the plurality of data signals within a left edge section and a right edge section of windows of the data signals, based on the offset information, and 
 wherein the first boot-up operation is a boot-up operation performed for a first time, and the second boot-up operation is a boot-up operation performed after the first boot-up operation. 
 
     
     
       9. The storage device of  claim 8 ,
 wherein the storage controller circuit is further configured such that, in the first training, the storage controller circuit detects a left edge (LE) of each of the plurality of data signals and a right edge (RE) of each of the plurality of data signals while shifting a data strobe signal as much as a tick time during the windows of the data signals, and 
 wherein the storage controller circuit is further configured such that, in the second training, the storage controller circuit sets a left edge (LE) section and a right edge (RE) section of the windows of the data signals based on the offset information, detects the LE of each of the plurality of data signals while shifting the data strobe signal as much as the tick time within the LE section, and detects the RE of each of the plurality of data signals while shifting the data strobe signal as much as the tick time within the RE section. 
 
     
     
       10. The storage device of  claim 8 , wherein the storage controller circuit is further configured to,
 store the offset information after performing the first training, and 
 load the offset information when performing the second training. 
 
     
     
       11. The storage device of  claim 8 , wherein the storage controller circuit is further configured such that, based on performing the first training and the second training, the storage controller circuit,
 sends a read command to the nonvolatile memory device through the plurality of data signals during a command output phase; 
 sends an address to the nonvolatile memory device through the plurality of data signals during an address output phase; and 
 receives pattern data from the nonvolatile memory device through the plurality of data signals during a data input phase. 
 
     
     
       12. The storage device of  claim 9 , wherein the storage controller circuit is further configured to calculate a center of a window of each of the plurality of data signals based on the detected LE and the detected RE of each of the plurality of data signals. 
     
     
       13. The storage device of  claim 9 , wherein the storage controller circuit comprises:
 a data strobe pad configured to receive the data strobe signal from the nonvolatile memory device; and 
 a delay locked loop circuit configured to shift the data strobe signal provided from the data strobe pad as much as the tick time. 
 
     
     
       14. The storage device of  claim 13 , wherein the storage controller circuit further includes:
 a plurality of data input/output pads configured to receive the plurality of data signals; and 
 a plurality of input delay circuits configured to delay the data signals provided from the input/output pads based on the offset information. 
 
     
     
       15. The storage device of  claim 8 , wherein the storage controller circuit is further configured to update the offset information based on a result of performing the second training. 
     
     
       16. A storage controller circuit comprising:
 a plurality of data input/output pads configured to receive a plurality of data signals; 
 a data strobe pad configured to receive a data strobe signal; and 
 a training circuit, 
 wherein the training circuit is configured such that, based on performance of a first boot-up operation, the training circuit performs first training on the plurality of data signals and generates offset information based on a result of the first training, 
 wherein the training circuit is further configured such that, based on performance of a second boot-up operation, the training circuit performs second training on the plurality of data signals within a left edge section and a right edge section of windows of the data signals based on the offset information, and 
 wherein the first boot-up operation is a boot-up operation performed for first time, and the second boot-up operations is a boot-up operation performed after the first boot-up operation. 
 
     
     
       17. The storage controller circuit of  claim 16 , wherein the training circuit is configured to store the offset information in one of a serial NOR flash memory, an electronic fuse (eFuse), an electrically erasable and programmable read only memory (EEPROM), a mask ROM, a serial programmable ROM (PROM), a flash memory or a one-time programmable (OTP) memory. 
     
     
       18. The storage controller circuit of  claim 16 ,
 wherein the training circuit is further configured to detect a left edge (LE) and a right edge (RE) of each of the plurality of data signals by repeatedly performing a detection operation while adjusting a delay amount of the data strobe signal, and 
 wherein the training circuit is further configured to perform the detection operation by,
 outputting a read command through the plurality of data signals during a command output phase, 
 outputting an address through the plurality of data signals during an address output phase, and 
 receiving pattern data through the plurality of data signals during a data input phase. 
 
 
     
     
       19. The storage controller circuit of  claim 18 , wherein the training circuit is further configured to set the left edge (LE) section and the right edge (RE) section of windows of the data signals based on the offset information, detects the LE of each of the plurality of data signals while shifting the data strobe signal as much as a tick time within the LE section, and detects the RE of each of the plurality of data signals while shifting the data strobe signal as much as the tick time within the RE section. 
     
     
       20. The storage controller circuit of  claim 16 , further comprising:
 a delay locked loop circuit configured to receive the data strobe signal from the data strobe pad and to adjust a delay amount of the data strobe signal in response to a clock control signal from the training circuit; and 
 a plurality of input delay circuits configured to receive the plurality of data signals from the plurality of data input/output pads and to adjust delay amounts of the plurality of data signals in response to an input data control signal from the training circuit.