Circuit and method for binary flag determination

Abstract

The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.

What is claimed is: 
     
       1. A method comprising:
 receiving, by a first EXCLUSIVE OR logic gate in an arithmetic and logic unit (ALU) circuit, a second masked binary datum and an add/subtract operation information; 
 generating, by the first EXCLUSIVE OR logic gate, a first intermediate output; 
 receiving, by a second EXCLUSIVE OR logic gate in the ALU circuit, a second mask for the second masked binary datum, and the add/subtract operation information; 
 generating, by the second EXCLUSIVE OR logic gate, a second intermediate output; 
 receiving, by a first adder circuit in the ALU circuit, the first intermediate output, a first masked binary datum, and the add/subtract operation information; 
 adding to or subtracting from the first masked binary datum, by the first adder circuit in the ALU circuit, the second masked binary datum to generate an output masked binary datum, in accordance with the add/subtract operation information; 
 receiving, by a second adder circuit in the ALU circuit, the second intermediate output, a first mask, and the add/subtract operation information; 
 adding to or subtracting from the first mask, by the second adder circuit in the ALU circuit, the second mask to generate an output mask, in accordance with the add/subtract operation information; 
 receiving, by a comparator circuit in the ALU, the output masked binary datum and the output mask; and 
 comparing, by the comparator circuit in the ALU circuit, the output masked binary datum and the output mask to determine a sign indicator bit of an output unmasked binary datum of the output masked binary datum, without any processing of the output unmasked binary datum itself. 
 
     
     
       2. The method according to  claim 1 , wherein the output masked binary datum is kept masked during the comparing. 
     
     
       3. The method according to  claim 1 , wherein the output unmasked binary datum is negative in accordance with its most significant bit being equal to “1.” 
     
     
       4. The method according to  claim 1 , wherein the output masked binary datum is masked by adding the output mask to the output unmasked binary datum. 
     
     
       5. The method according to  claim 4 , wherein the sign indicator bit is equal to “1” in accordance with the following condition being met:
   ( H _ M+CH _ M* 2 n )≥( MH+ 2 n-1 )
 
 where:
 H_M is the output masked binary datum; 
 “+” represents an addition operation; 
 CH_M is a carry digit that may appear during a masking operation of the output masked binary datum H_M; 
 MH is the output mask; and 
 n is a number of bits in the output masked binary datum and the output mask. 
 
 
     
     
       6. The method according to  claim 5 , wherein the carry digit is equal to “1” in accordance with the following condition is met:
     H _ M<MH.    
 
     
     
       7. The method according to  claim 5 , wherein the carry digit is equal to “0” in accordance with the following condition not being met:
     H _ M<MH.    
 
     
     
       8. An arithmetic and logic unit (ALU) circuit comprising:
 an add/subtract circuit to comprising:
 a first EXCLUSIVE OR logic gate configured to receive a second masked binary datum, and an add/subtract operation information, and generate a first intermediate output; 
 a second EXCLUSIVE OR logic gate configured to receive a second mask for the second masked binary datum, and the add/subtract operation information, and generate a second intermediate output; 
 a first adder circuit coupled to the first EXCLUSIVE OR logic gate, and configured to receive the first intermediate output, a first masked binary datum, and the add/subtract operation information, and generate an output masked binary datum representing the second masked binary datum added to or subtracted from the first masked binary datum, in accordance with the add/subtract operation information; and 
 a second adder circuit coupled to the second EXCLUSIVE OR logic gate, and configured to receive the second intermediate output, a first mask, and the add/subtract operation information, and generate an output mask representing the second mask added to or subtracted from the first mask, in accordance with the add/subtract operation information; and 
 a comparator circuit coupled to the first and second adder circuits, and configured to compare the output masked binary datum and the output mask to determine a sign indicator bit of an output unmasked binary datum of the output masked binary datum, without any processing of the output unmasked binary datum itself. 
 
 
     
     
       9. The ALU circuit according to  claim 8 , wherein the output masked binary datum is kept masked during the comparison. 
     
     
       10. The ALU circuit according to  claim 8 , wherein the output unmasked binary datum is negative in accordance with its most significant bit being equal to “1.” 
     
     
       11. The ALU circuit according to  claim 8 , wherein the output masked binary datum is masked by adding the output mask to the output unmasked binary datum. 
     
     
       12. The ALU circuit according to  claim 11 , wherein the sign indicator bit is equal to “1” in accordance with the following condition being met:
   ( H _ M+CH _ M* 2 n )≥( MH+ 2 n-1 )
 
 where:
 H_M is the output masked binary datum; 
 “+” represents an addition operation; 
 CH_M is a carry digit that may appear during a masking operation of the output masked binary datum H_M; 
 MH is the output mask; and 
 n is a number of bits in the output masked binary datum and the output mask. 
 
 
     
     
       13. The ALU circuit according to  claim 12 , wherein the carry digit is equal to “1” in accordance with the following condition is met:
     H _ M<MH.    
 
     
     
       14. The ALU circuit according to  claim 12 , wherein the carry digit is equal to “0” in accordance with the following condition not being met:
     H _ M<MH.    
 
     
     
       15. A processor comprising:
 an arithmetic and logic unit (ALU) circuit comprising:
 an add/subtract circuit to comprising:
 a first EXCLUSIVE OR logic gate configured to receive a second masked binary datum, and an add/subtract operation information, and generate a first intermediate output; 
 a second EXCLUSIVE OR logic gate configured to receive a second mask for the second masked binary datum, and the add/subtract operation information, and generate a second intermediate output; 
 a first adder circuit coupled to the first EXCLUSIVE OR logic gate, and configured to receive the first intermediate output, a first masked binary datum, and the add/subtract operation information, and generate an output masked binary datum representing the second masked binary datum added to or subtracted from the first masked binary datum, and an output masked binary datum carry digit, in accordance with the add/subtract operation information; and 
 a second adder circuit coupled to the second EXCLUSIVE OR logic gate, and configured to receive the second intermediate output, a first mask, and the add/subtract operation information, and generate an output mask representing the second mask added to or subtracted from the first mask, and an output mask carry digit, in accordance with the add/subtract operation information; 
 
 a first comparator circuit coupled to the first and second adder circuits, and configured to compare the output masked binary datum and the output mask to determine a sign indicator bit of an output unmasked binary datum of the output masked binary datum, without any processing of the output unmasked binary datum itself; and 
 second and third comparator circuits, wherein the first, second and third comparator circuits are configured to process the first masked binary datum, the first mask for the first masked binary datum, the second masked binary datum, the second mask for the second masked binary datum, the add/subtract operation information, the output masked binary datum, the output mask, the output masked binary datum carry digit, and the output mask carry digit to generate a carry digit indicator bit, a nil value indicator bit, and an overflow indicator bit. 
 
 
     
     
       16. The processor according to  claim 15 , wherein the output masked binary datum is kept masked during the comparison. 
     
     
       17. The processor according to  claim 15 , wherein the output unmasked binary datum is negative in accordance with its most significant bit being equal to “1.” 
     
     
       18. The processor according to  claim 15 , wherein the output masked binary datum is masked by adding the output mask to the output unmasked binary datum. 
     
     
       19. The processor according to  claim 18 , wherein the sign indicator bit is equal to “1” in accordance with the following condition being met:
   ( H _ M+CH _ M* 2 n )≥( MH+ 2 n-1 )
 
 where:
 H_M is the output masked binary datum; 
 “+” represents an addition operation; 
 CH_M is a first carry digit that may appear during a masking operation of the output masked binary datum H_M; 
 MH is the output mask; and 
 n is a number of bits in the output masked binary datum and the output mask. 
 
 
     
     
       20. The processor according to  claim 19 , wherein the first carry digit is equal to “1” in accordance with the following condition is met:
     H _ M<MH.    
 
     
     
       21. The processor according to  claim 19 , wherein the first carry digit is equal to “0” in accordance with the following condition not being met:
     H _ M<MH.