Watchdog for addressing deadlocked states

Abstract

The described techniques address deadlocking issues associated with interconnected hardware devices that share bus lines associated with a digital communication interface. A watchdog-based solution is described that may be implemented internally within the interconnected hardware devices or, alternatively, as an external component. The watchdog circuity may monitor a logic state of one or more internal connections of a hardware device and cause one or more portions of the hardware device to reset when a deadlock condition is detected using this internal monitoring.

What is claimed is: 
     
       1. A device, comprising:
 a transistor coupled to a bus line external to the device and to logic circuitry internal to the device, the transistor being configured to change a logic state of the bus line from a first logic state to a second logic state in response to an assertion of a control signal by the logic circuitry; and 
 watchdog circuitry internal to the device, the watchdog circuitry being configured to provide an overtime signal to the logic circuitry when the control signal remains asserted at the same logic state in excess of a threshold timeout period. 
 
     
     
       2. The device of  claim 1 , wherein the transistor is coupled to the bus line in an open drain configuration or a push-pull configuration. 
     
     
       3. The device of  claim 1 , wherein the bus line is a clock line that is connected to the device and to a second device. 
     
     
       4. The device of  claim 3 , wherein the clock line is used in accordance with an I2C communication protocol to enable the device and the second device to communicate with one another. 
     
     
       5. The device of  claim 1 , wherein the overtime signal provided by the watchdog circuitry causes one or more portions of the device to reset. 
     
     
       6. The device of  claim 5 , wherein upon the one or more portions of the device being reset, the control signal changes to a logic state that is different than the same logic state at which the control signal remained asserted in excess of the threshold timeout period. 
     
     
       7. The device of  claim 1 , wherein the watchdog circuitry is configured to initiate a timer based on detecting a change in the logic state of the control signal. 
     
     
       8. The device of  claim 1 , wherein the watchdog circuitry is configured to operate using at least one of a different oscillator or a different power supply than the logic circuitry. 
     
     
       9. The device of  claim 1 , wherein the transistor, the watchdog circuitry, and the logic circuitry are implemented on a same semiconductor chip. 
     
     
       10. The device of  claim 1 , wherein the transistor receives the control signal from the logic circuitry via a control line, and
 wherein the watchdog circuitry is connected to the control line via a monitoring line. 
 
     
     
       11. A system, comprising:
 a first device configured to selectively drive a bus line; and 
 a second device coupled to the first device via the bus line, the second device being configured to selectively drive the bus line and including:
 a transistor coupled to the bus line and to logic circuitry internal to the second device, the transistor being configured to change a logic state of the bus line from a first logic state to a second logic state in response to an assertion of a control signal by the logic circuitry indicating that the second device is to drive the bus line; and 
 watchdog circuitry internal to the second device, the watchdog circuitry being configured to monitor a logic state of the control signal, and to provide an overtime signal to the logic circuitry when the control signal remains asserted at the same logic state in excess of a threshold timeout period. 
 
 
     
     
       12. The system of  claim 11 , wherein the first device is a master device, and
 wherein the second device is a slave device. 
 
     
     
       13. The system of  claim 12 , wherein the control signal is one of (i) an interrupt signal that signals an event to the master device, or (ii) a clock stretching signal that prevents the master device from communicating with the slave device in excess of a threshold communication rate. 
     
     
       14. A method, comprising:
 changing, via a transistor, a logic state of a bus line from a first logic state to a second logic state in response to an assertion of a control signal by a logic circuitry internal to a first device, the transistor being coupled to (i) a bus line external to the first device, and (ii) the logic circuitry; and 
 outputting, via watchdog circuitry internal to the first device, an overtime signal when the control signal remains asserted at the same logic state in excess of a threshold timeout period. 
 
     
     
       15. The method of  claim 14 , further comprising:
 coupling the transistor to the bus line in an open drain configuration or a push-pull configuration. 
 
     
     
       16. The method of  claim 14 , further comprising:
 coupling the bus line to a second device as a clock line that is coupled to the first device and to the second device. 
 
     
     
       17. The method of  claim 16 , further comprising:
 asserting, via the logic circuitry, the control signal as one of (i) an interrupt signal when the first device signals an event to the second device, or (ii) a clock stretching signal that prevents the second device from communicating with the first device in excess of a threshold communication rate. 
 
     
     
       18. The method of  claim 14 , wherein the overtime signal provided by the watchdog circuitry causes one or more portions of the first device to reset, thereby changing the control signal to a logic state that is different than the same logic state at which the control signal remained asserted in excess of the threshold timeout period. 
     
     
       19. The method of  claim 14 , further comprising:
 based on detecting a change in the logic state of the control signal, initiating a timer via the watchdog circuitry. 
 
     
     
       20. The method of  claim 14 , further comprising:
 coupling the watchdog circuitry to at least one of a different oscillator or a different power supply than the logic circuitry. 
 
     
     
       21. The device of  claim 1 , wherein the overtime signal provided by the watchdog circuitry causes the logic circuitry to unassert the control signal. 
     
     
       22. The device of  claim 21 , wherein the watchdog circuitry is configured to initiate a counter that (i) starts counting up to the threshold timeout period upon the logic circuitry asserting the control signal, and (ii) resets upon the logic circuitry unasserting the control signal.