Fractional phase locked loop (PLL) with digital control driven by clock with higher frequency than PLL feedback signal

Abstract

A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

What is claimed: 
     
       1. A phase locked loop (PLL), comprising:
 a fractional frequency divider; 
 a phase detector including a first input configured to receive a reference clock or signal, and a second input coupled to an output of the fractional frequency divider; 
 a voltage-controlled oscillator (VCO) including an input coupled to an output of the phase detector, and an output coupled to a first input of the fractional frequency divider; 
 a digital control circuit comprising a frequency multiplier including a first input coupled to the output of the fractional frequency divider, wherein the digital control circuit includes an output coupled to a second input of the fractional frequency divider; and 
 an integer frequency divider including an input coupled to the output of the VCO and an output coupled to the input of the fractional frequency divider. 
 
     
     
       2. The PLL of  claim 1 , wherein the digital control circuit further comprises a delta-sigma modulator including an input coupled to an output of the frequency multiplier. 
     
     
       3. The PLL of  claim 1 , wherein the digital control circuit further comprises a spread spectrum clock (SSC) including a first input coupled to the output of the frequency multiplier. 
     
     
       4. The PLL of  claim 3 , wherein the SSC includes a second input configured to receive a second signal to set an integer divisor for the fractional frequency divider. 
     
     
       5. The PLL of  claim 3 , wherein the SSC includes a second input configured to receive a second signal to set a fractional divisor for the fractional frequency divider. 
     
     
       6. The PLL of  claim 1 , wherein the frequency multiplier comprises a frequency doubler. 
     
     
       7. The PLL of  claim 1 , further comprising a charge pump including an input coupled to the output of the phase detector and an output coupled to the input of the VCO. 
     
     
       8. The PLL of  claim 1 , further comprising a filter including an input coupled to the output of the phase detector and an output coupled to the input of the VCO. 
     
     
       9. The PLL of  claim 1 , wherein the first input of the phase detector is coupled to an output of a receive circuit to receive the reference signal therefrom. 
     
     
       10. A method, comprising:
 generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; 
 generating an output clock based on the first signal; 
 generating an intermediate feedback clock including frequency dividing the output clock; 
 fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; 
 generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock; and 
 generating the sampling clock including frequency multiplying the feedback clock. 
 
     
     
       11. The method of  claim 10 , further comprising generating the sampling clock including frequency doubling the feedback clock. 
     
     
       12. The method of  claim 10 , wherein generating the intermediate feedback clock includes frequency dividing the output clock by an integer. 
     
     
       13. The method of  claim 10 , wherein generating the digital control signal comprises delta-sigma modulating a second signal using the sampling clock. 
     
     
       14. A method, comprising:
 generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; 
 generating an output clock based on the first signal; 
 generating an intermediate feedback clock including frequency dividing the output clock; 
 fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and 
 generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock, 
 wherein generating the digital control signal comprises applying spread spectrum to a second signal using the sampling clock to generate a third signal. 
 
     
     
       15. The method of  claim 14 , wherein generating the digital control signal further comprises delta-sigma modulating the third signal using the sampling clock. 
     
     
       16. The method of  claim 15 , wherein the second signal sets a fractional divisor for the fractionally frequency dividing. 
     
     
       17. The method of  claim 15 , wherein the second signal sets an integer divisor for the fractionally frequency dividing. 
     
     
       18. The method of  claim 10 , wherein generating the first signal comprises driving a charge pump based on the comparison of the phase of the reference clock or signal to the phase of the feedback clock. 
     
     
       19. The method of  claim 18 , further comprising integrating a second signal generated by the charge pump, wherein generating the output clock is based on the second signal. 
     
     
       20. A data receiver, comprising:
 a receiver circuit configured to generate a serial data signal based on a transmit data signal received from a data transmitter via one or more transmission lines; 
 a clock and data recovery (CDR) configured to generate a receive clock based on the serial data signal; and 
 a deserializer configured to generate a set of parallel data signals based on the serial data signal using the receive clock; 
 wherein the CDR comprises:
 a fractional frequency divider; 
 a phase detector including a first input configured to receive the serial data signal, and a second input coupled to an output of the fractional frequency divider; 
 a voltage-controlled oscillator (VCO) including an input coupled to an output of the phase detector, and an output coupled to a first input of the fractional frequency divider; and 
 
 a digital control circuit comprising a frequency multiplier including an input coupled to the output of the fractional frequency divider, wherein the digital control circuit includes an output coupled to a second input of the fractional frequency divider.