Semiconductor device and method for forming the same

Abstract

A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate having a memory region and a logic region; 
 a first dielectric layer on the substrate; 
 a first conductive structure and a second conductive structure formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate; 
 a memory cell formed on the first dielectric layer and directly contacting a top surface of the first conductive structure; 
 a first cap layer continuously covering a top surface and a sidewall of the memory cell and directly contacting a top surface of the second conductive structure; 
 a second dielectric layer on the first cap layer; and 
 a third conductive structure formed in the second dielectric layer and through the first cap layer to contact the memory cell. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the first conductive structure, the second conductive structure and the third conductive structure comprise a same metal. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the top surface of the first conductive structure and the top surface of the second conductive structure are flush with a surface of the first dielectric layer. 
     
     
       4. The semiconductor device according to  claim 1 , further comprising a second cap layer formed on the second dielectric layer and directly covering a top surface of the third conductive structure, wherein the first cap layer and the second cap layer comprise a same dielectric material. 
     
     
       5. The semiconductor device according to  claim 4 , wherein the first cap layer and the second cap are made of nitride doped silicon carbide, the first dielectric layer and the second dielectric layer are made of low-k dielectric materials. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the third conductive structure comprises:
 a lower portion directly contacting the memory cell; and 
 an upper portion on the lower portion, wherein a width of the upper portion is larger than a width of the lower portion. 
 
     
     
       7. The semiconductor device according to  claim 1 , wherein the third conductive structure comprises a straight sidewall extending from a surface of the second dielectric layer to the top surface of the memory cell. 
     
     
       8. The semiconductor device according to  claim 1 , further comprises a fourth conductive structure formed in the second dielectric layer and through the first cap layer to contact the second conductive structure, wherein a top surface of the third conductive structure and a top surface of the fourth conductive structure are flush with a surface of the second dielectric layer. 
     
     
       9. The semiconductor device according to  claim 8 , wherein the fourth conductive structure comprises:
 a lower portion directly contacting the second conductive structure; and 
 an upper portion on the lower portion, wherein a width of the upper portion is larger than a width of the lower portion. 
 
     
     
       10. The semiconductor device according to  claim 9 , wherein a bottom surface of the upper portion of the fourth conductive structure is lower than the top surface of the memory cell. 
     
     
       11. The semiconductor device according to  claim 1 , wherein the memory cell comprises:
 a bottom electrode; 
 a memory layer on the bottom electrode; and 
 a top electrode on the memory layer, wherein the bottom electrode directly contacts the first conductive structure.