Semiconductor device

Abstract

A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

The invention claimed is: 
     
       1. A semiconductor device that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device comprising:
 a semiconductor layer; 
 a vertical field-effect transistor provided in a first region in the semiconductor layer; and 
 a drain lead-out region provided in a second region adjacent to the first region in the semiconductor layer in a plan view of the semiconductor layer, 
 wherein the semiconductor layer is in a rectangular shape in the plan view, 
 when, in the plan view, out of longer sides of the semiconductor layer, a longer side included in the first region and a longer side included in the second region are referred to as one longer side and an other longer side, respectively, and out of shorter sides of the semiconductor layer, a shorter side defining a first vertex with the one longer side is referred to as one shorter side, and a shorter side opposite to the one shorter side is referred to as an other shorter side, a border line between the first region and the second region is a straight line parallel to the longer sides of the semiconductor layer in the plan view, 
 the first region includes a plurality of source pads and one or more gate pads on a surface of the semiconductor layer, 
 the second region includes a plurality of drain pads on the surface of the semiconductor layer, 
 at least one gate pad among the one or more gate pads is disposed to dispose none of the plurality of source pads between (i) the at least one gate pad and (ii) the one longer side and the one shorter side in the plan view, 
 at least one drain pad among the plurality of drain pads is in a same shape as the at least one gate pad in the plan view, and is disposed close to a second vertex of the semiconductor layer in the plan view, the second vertex being diagonally opposite to the first vertex, 
 the plurality of source pads include a plurality of source pads that are, in the plan view, in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer, 
 the plurality of drain pads include a drain pad that is, in the plan view, in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer, 
 the plurality of source pads in the rectangular shape or the obround shape are disposed in stripes at regular intervals in the plan view, and 
 in the plan view, spaces between the plurality of source pads in the rectangular shape or the obround shape are equal to a space between a source pad and the drain pad in the rectangular shape or the obround shape that are opposite to each other across the border line, the source pad being included in the plurality of source pads in the rectangular shape or the obround shape. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein in the plan view, a center of the at least one gate pad and a center of the at least one drain pad are on a diagonal line of the semiconductor layer connecting the first vertex and the second vertex. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 wherein in the plan view, the border line intersects each of the one shorter side and the other shorter side at an intersection point that divides the semiconductor layer at a ratio in a range of 2:1 to 4:1 in a shorter side direction of the semiconductor layer, and 
 in the plan view, the second region has an area smaller than an area of the first region. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the semiconductor layer is in a square shape in the plan view, and 
 in the plan view, the first region is in a rectangular shape having a length ratio between longer sides and shorter sides of the first region that is in a range of 5:4 to 3:2. 
 
     
     
       5. The semiconductor device according to  claim 1 ,
 wherein in the plan view, the plurality of source pads in the rectangular shape or the obround shape include at least one source pad having a length in the longitudinal direction equal to an entire length of the border line minus any empty space in which the at least one source pad is not disposed. 
 
     
     
       6. The semiconductor device according to  claim 1 ,
 wherein in the plan view:
 the plurality of source pads, the at least one gate pad, and the plurality of drain pads have a same width in a shorter side direction of the semiconductor layer; and 
 spaces between the plurality of source pads are less than or equal to widths of the plurality of source pads. 
 
 
     
     
       7. The semiconductor device according to  claim 1 ,
 wherein the semiconductor layer is in a square shape in the plan view, and 
 in the plan view, a configuration formed on the surface of the semiconductor layer by the plurality of source pads, the at least one gate pad, and the plurality of drain pads has a 180° rotational symmetry and does not have a 90° rotational symmetry about a point intersected by diagonal lines of the semiconductor layer.