Memory system with a predictable read latency from media with a long write latency

Abstract

Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.

What is claimed: 
     
       1. A method for operating a memory system comprising at least one array of N rows of tiles and M columns of tiles, wherein each of N and M is an integer, wherein each of the tiles is configured to store data corresponding to at least one cache line associated with a host, and wherein each of the tiles comprises memory cells, the method comprising:
 in response to a write command from a host, initiating writing of a first cache line to a first tile in a first row of the N rows of tiles, a second cache line to a second tile in a second row of the N rows of tiles, a third cache line to a third tile in a third row of the N rows of tiles, and a fourth cache line in a fourth row of the N rows of tiles, and having at least N cache lines to be written in response to the write command from the host; and 
 in response to a read command from the host, initiating reading of data stored in an entire row of tiles, and haying at least M cache lines to be read in response to the read command from the host. 
 
     
     
       2. The method of  claim 1 , wherein the first tile, the second tile, the third tile, and the fourth tile do not share a column. 
     
     
       3. The method of  claim 1 , wherein the memory system further comprises an additional column of tiles, wherein the additional column of tiles is configured to store parity bits. 
     
     
       4. The method of  claim 3 , wherein a selection of a location of a tile in a row of tiles to store the parity bits is based on a logical address associated with the location of the tile. 
     
     
       5. The method of  claim 1 , further comprising mapping a logical address associated with a cache line to a physical address associated with the cache line in a manner to reduce wear caused by repeated writing of memory cells associated with the tiles. 
     
     
       6. The method of  claim 1 , wherein the memory system further comprises N decoders, wherein each decoder corresponds to a respective row of the N rows of tiles. 
     
     
       7. A method for operating a memory system comprising at least one array of N rows of tiles and M columns of tiles, wherein each of N and M is an integer, wherein each of the tiles is configured to store data corresponding to at least one cache line associated with a host, and wherein each of the tiles comprises memory cells, the method comprising:
 in response to a write command from the host, initiating writing of a first cache line to a first tile in a first row of the N rows of tiles, a second cache line to a second tile in a second row of the N rows of tiles, a third cache line to a third tile in a third row of the N rows of tiles, and a fourth cache line in a fourth row of the N rows of tiles, and having at least N cache lines to be written in response to the write command from the host, and generate a first bit-wise parity for tiles in the first row of the N rows of tiles, a second bit-wise parity for tiles in the second row of the N rows of tiles, a third bit-wise parity for tiles in the third row of the N rows of tiles, and a fourth bit-wise parity for tiles in the fourth row of the N rows of tiles; and 
 in response to a read command from the host, initiating reading of data stored in an entire row of tiles, and having at least M cache lines to be read in response to the read command from the host. 
 
     
     
       8. The method of  claim 7 , wherein the first tile, the second tile, the third tile, and the fourth tile do not share a column. 
     
     
       9. The method of  claim 7 , wherein the first tile, the second tile, the third tile, and the fourth tile share a column. 
     
     
       10. The method of  claim 7 , wherein the parity bits corresponding to the first bit-wise parity, the second bit-wise parity, the third bit-wise parity, and the fourth bit-wise parity are stored in a separate memory. 
     
     
       11. The method of  claim 7 , wherein the parity bits corresponding to the first bit-wise parity, the second bit-wise parity, the third bit-wise parity, and the fourth bit-wise parity are stored in tiles. 
     
     
       12. The method of  claim 7 , further comprising mapping a logical address associated with a cache line to a physical address associated with the cache line in a manner to reduce wear caused by repeated writing of memory cells associated with the tiles. 
     
     
       13. A method for operating a memory system comprising at least one array of N rows of tiles and M columns of tiles, wherein each of N and M is an integer, wherein each of the tiles is configured to store data corresponding to at least one cache line associated with a host, and wherein each of the tiles comprises memory cells, the method comprising:
 in response to a read command from the host attempting to read data from a selected tile, initiating reading of data stored in one row of the N rows of tiles, except for the selected tile from among the tiles in the one row of the N rows of tiles, while completing writing of data to the selected tile from among the tiles in the one row of the N rows of tiles; and 
 in response to the read command from the host, initiating reconstruction of data stored in the selected tile from among the tiles in the one row of the N rows of tiles using data from the tiles in the one row of the N rows of tiles, except for data from the selected tile, and parity bits corresponding to the one row of the N rows of tiles being read in response to the read command from the host. 
 
     
     
       14. The method of  claim 13 , wherein the memory system further comprises N×M decoders, and wherein each decoder corresponds to a respective tile. 
     
     
       15. The method of  claim 14 , wherein at least the selected tile from among the tiles in the one of N rows of tiles is coupled to a set of global wordlines shared across at least the tiles in the one of the N rows of tiles and a set of local wordlines for use with the selected tile from among the tiles in the one of N rows of tiles. 
     
     
       16. The method of  claim 13 , wherein the memory system further comprises a first set of voltage driver circuits and latches coupled to a set of global wordlines and a second set of voltage driver circuits and latches coupled to a set of local wordlines. 
     
     
       17. The method of  claim 16 , wherein the memory system further comprises circuitry configured to latch, in one of the latches, a state of any global wordlines associated with the selected tile from among the tiles in the one of N rows of tiles, sever a connection with the global wordlines, and drive, using one of the voltage driver circuits, any local wordlines associated with the selected tile from among the tiles in the one of N rows of tiles. 
     
     
       18. The method of  claim 13 , wherein the memory system further comprises K decoders, wherein K is an integer multiple of N, and wherein at least two decoders from among the K decoders correspond to a respective row of the N rows of tiles. 
     
     
       19. The method of  claim 18 , wherein at least the selected tile from among the tiles in the one of N rows of tiles is coupled to a set of global wordlines shared across at least the tiles in the one of the N rows of tiles and a set of local wordlines for use with the selected tile from among the tiles in the one of N rows of tiles. 
     
     
       20. The method of  claim 18 , wherein the memory system further comprises a first set of voltage driver circuits and latches coupled to a set of global wordlines and a second set of voltage driver circuits and latches coupled to a set of local wordlines.