Through silicon via fabrication

Abstract

One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.

The invention claimed is: 
     
       1. A process comprising:
 depositing a top mask onto a silicon wafer, the top mask comprising a first silicon dioxide layer; 
 depositing a bottom mask onto the bottom of the silicon wafer; 
 photopatterning a through silicon via pattern and etching a through silicon via into the top mask; 
 etching the through silicon via, using the through silicon via pattern, through the silicon wafer; 
 growing a second thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; 
 etching the second thermal silicon dioxide layer; 
 growing a third thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; 
 depositing a plating seed layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; 
 electroplating a copper layer in the through silicon via; 
 depositing a fourth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; 
 etching the fourth silicon dioxide layer; 
 depositing a fifth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; 
 etching the fifth silicon dioxide layer; 
 depositing a sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer; 
 chemomechanically polishing (CMP) the sixth silicon dioxide layer down to the copper layer; and 
 chemomechanically polishing the copper layer. 
 
     
     
       2. The process of  claim 1 , comprising:
 removing the top mask and the bottom mask from the silicon wafer; 
 depositing an adhesion layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; and 
 depositing a second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer. 
 
     
     
       3. The process of  claim 2 , wherein the depositing the adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer comprises depositing approximately 2500 Angstroms of titanium followed by approximately 3 micrometers of a copper seed layer on the top of the silicon wafer and the bottom of the silicon wafer, thereby narrowing the through silicon via to approximately 19.4 micrometers. 
     
     
       4. The process of  claim 2 , wherein the second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer comprises a titanium tungsten layer having a thickness of approximately 2000 angstroms. 
     
     
       5. The process of  claim 2 , wherein the depositing the adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer comprises depositing approximately 2000 A titanium tungsten followed by approximately 3 micrometers of a copper seed layer on the top of the silicon wafer and the bottom of the silicon wafer, thereby narrowing the through silicon via to approximately 19.4 micrometers; and wherein the second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer comprises a titanium nitride layer of approximately 1000 Angstroms, the second adhesion layer deposited by atomic layer deposition (ALD). 
     
     
       6. The process of  claim 1 , wherein the silicon wafer is approximately 300 micrometers thick. 
     
     
       7. The process of  claim 1 , wherein the top mask is approximately 1-7 micrometers thick. 
     
     
       8. The process of  claim 1 , wherein the bottom mask comprises an aluminum layer, and wherein the aluminum layer is approximately 1-2 micrometers thick. 
     
     
       9. The process of  claim 1 , wherein the through silicon via comprises rounded-corner rectangles or ovals comprising dimensions of approximately 20 micrometers to 50 micrometers or 20 micrometers to 70 micrometers. 
     
     
       10. The process of  claim 1 , wherein the etching the through silicon via through the silicon wafer comprises etching to the bottom mask, and comprises deep reactive-ion etching (DRIE), and wherein the through silicon via is approximately 20 micrometers wide. 
     
     
       11. The process of  claim 1 , wherein the second thermal silicon dioxide layer is approximately 1.5 micrometers thick. 
     
     
       12. The process of  claim 1 , wherein the etching the second thermal silicon dioxide layer comprises etching the second thermal silicon dioxide layer off the silicon wafer, and comprises a wet etching, wherein the wet etching widens the through silicon via to approximately 21 micrometers, and wherein wet etching smooths scallops on the silicon wafer. 
     
     
       13. The process of  claim 1 , wherein the third silicon dioxide layer comprises a passivation layer, wherein the third thermal silicon dioxide layer is approximately 1.5 micrometers thick, and wherein the growing the third thermal silicon dioxide layer narrows the through silicon via to approximately 19.5 micrometers, and wherein the third silicon dioxide layer comprises a chemomechanically polished (CMP) stop layer. 
     
     
       14. The process of  claim 1 , wherein the electroplating the copper layer in the through silicon via results in the copper layer penetrating into the through silicon via to a depth of approximately 3 micrometers and a narrowing of the through silicon via to approximately 13.4 micrometers. 
     
     
       15. The process of  claim 1 , wherein the depositing the fourth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer comprises a plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry, thereby narrowing the through silicon via to approximately 3.4 micrometers, and resulting in the fourth silicon dioxide layer being approximately 5 micrometers thick; and wherein the etching the fourth silicon dioxide layer removes a portion of the fourth silicon dioxide layer and comprises a directional dry etch, thereby removing approximately 4.5 micrometers of the fourth silicon dioxide layer, and resulting in the through silicon via being approximately 12.4 micrometers near the top of the silicon wafer and the through silicon via being approximately 4 micrometers near a midpoint of the through silicon via and near the bottom of the silicon wafer. 
     
     
       16. The process of  claim 1 , wherein the depositing the fifth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer comprises a plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry, thereby narrowing the through silicon via to approximately 2.4 micrometers at the top of the silicon wafer, closing the through silicon via near the top of the silicon wafer, a midpoint of the silicon wafer, and the bottom of the silicon wafer, and resulting in a fifth silicon dioxide layer that is approximately 5 micrometers thick; and wherein the etching the fifth silicon dioxide layer removes a portion of the fifth silicon dioxide layer and comprises a directional dry etch, thereby removing approximately 4.5 micrometers of the fifth silicon dioxide layer, and resulting in the through silicon via having a thickness of approximately 12.4 micrometers at the top of the silicon wafer and closing the through silicon via within the silicon wafer and at the bottom of the silicon wafer. 
     
     
       17. The process of  claim 1 , wherein the depositing the sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer comprises a plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry, thereby closing the through silicon via at the top of the silicon wafer, a midpoint of the silicon wafer, and the bottom of the silicon wafer, and resulting in a sixth silicon dioxide layer that is approximately 5 micrometers thick. 
     
     
       18. The process of  claim 1 , comprising coupling a device to the through silicon via at the top layer of the silicon wafer or coupling a device to the through silicon via at the bottom layer of the silicon wafer. 
     
     
       19. The process of  claim 1 , comprising chemomechanically polishing (CMP) the sixth silicon dioxide layer down to the copper layer on the top of the silicon wafer and the bottom of the silicon wafer. 
     
     
       20. The process of  claim 1 , comprising chemomechanically polishing the copper layer, the first adhesion layer, and the second adhesion layer down to the third silicon dioxide layer.