Charge transfer between gate terminals of sub-threshold current reduction circuit transistors and related apparatuses and methods

Abstract

Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.

What is claimed is: 
     
       1. An apparatus, comprising:
 a first input terminal and a second input terminal; 
 a first output terminal and a second output terminal, the first output terminal electrically connected to a pull-up gate terminal of at least one pull-up sub-threshold current reduction circuit (SCRC) transistor, the second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor; 
 a first resistive path between the first input terminal and the first output terminal; 
 a second resistive path between the second input terminal and the second output terminal; and 
 a charge transfer gate electrically connected between the first resistive path and the second resistive path, the charge transfer gate electrically controllable to selectively transfer charge between the pull-up gate terminal and the pull-down gate terminal. 
 
     
     
       2. The apparatus of  claim 1 , wherein the first resistive path includes a first resistor electrically connected between a first intermediate node and the first output terminal. 
     
     
       3. The apparatus of  claim 2 , wherein the second resistive path includes a second resistor electrically connected between a second intermediate node and the second output terminal. 
     
     
       4. The apparatus of  claim 3 , wherein the first resistive path includes a third resistor electrically connected between the first input terminal and the first intermediate node. 
     
     
       5. The apparatus of  claim 4 , wherein the second resistive path includes a fourth resistor electrically connected between the second input terminal and the second intermediate node. 
     
     
       6. The apparatus of  claim 5 , wherein the charge transfer gate is electrically connected between the first intermediate node and the second intermediate node. 
     
     
       7. The apparatus of  claim 1 , wherein the charge transfer gate includes a metal-oxide-semiconductor field effect transistor (MOSFET). 
     
     
       8. The apparatus of  claim 1 , further comprising an SCRC pre-drive circuit, the SCRC pre-drive circuit configured to:
 operate in an SCRC off operational state; 
 operate in an SCRC on operational state; and 
 maintain deactivated during a charge transfer period of time at transitions between the SCRC off operational state and the SCRC on operational state; 
 wherein the charge transfer gate is configured to transfer charge between the pull-up gate terminal of the at least one pull-up SCRC transistor and the pull-down gate terminal of the at least one pull-down SCRC transistor during the charge transfer period of time. 
 
     
     
       9. The apparatus of  claim 8 , wherein a control circuitry is configured to operate the SCRC pre-drive circuit in the SCRC off operational state by:
 maintaining asserted a first pull-up signal on a gate terminal of a first pull-up transistor of the SCRC pre-drive circuit; and 
 maintaining de-asserted a first pull-down signal on a gate terminal of a first pull-down transistor of the SCRC pre-drive circuit. 
 
     
     
       10. The apparatus of  claim 9 , wherein the control circuitry is configured to operate the SCRC pre-drive circuit in the SCRC off operational state by:
 maintaining de-asserted a second pull-up signal on a gate terminal of a second pull-up transistor of the SCRC pre-drive circuit; and 
 maintaining asserted a second pull-down signal on a gate terminal of a second pull-down transistor of the SCRC pre-drive circuit. 
 
     
     
       11. The apparatus of  claim 8 , wherein a control circuitry is configured to operate the SCRC pre-drive circuit in the SCRC on operational state by:
 maintaining de-asserted a first pull-up signal on a gate terminal of a first pull-up transistor of the SCRC pre-drive circuit; and 
 maintaining asserted a first pull-down signal on a gate terminal of a first pull-down transistor of the SCRC pre-drive circuit. 
 
     
     
       12. The apparatus of  claim 11 , wherein the control circuitry is configured to operate the SCRC pre-drive circuit in the SCRC on operational state by:
 maintaining asserted a second pull-up signal on a gate terminal of a second pull-up transistor of the SCRC pre-drive circuit; and 
 maintaining de-asserted a second pull-down signal on a gate terminal of a second pull-down transistor of the SCRC pre-drive circuit. 
 
     
     
       13. The apparatus of  claim 8 , wherein a control circuitry is configured to maintain the SCRC pre-drive circuit deactivated by:
 maintaining de-asserted a first pull-up signal on a gate terminal of a first pull-up transistor of the SCRC pre-drive circuit; and 
 maintaining de-asserted a first pull-down signal on a gate terminal of a first pull-down transistor of the SCRC pre-drive circuit. 
 
     
     
       14. The apparatus of  claim 13 , wherein the control circuitry is configured to maintain the SCRC pre-drive circuit deactivated by:
 maintaining de-asserted a second pull-up signal on a gate terminal of a second pull-up transistor of the SCRC pre-drive circuit; and 
 maintaining de-asserted a second pull-down signal on a gate terminal of a second pull-down transistor of the SCRC pre-drive circuit. 
 
     
     
       15. The apparatus of  claim 8 , wherein a control circuitry is configured to control the charge transfer gate to transfer the charge between the pull-up gate terminal of the at least one pull-up SCRC transistor and the pull-down gate terminal of the at least one pull-down SCRC transistor by asserting a charge transfer control signal on a gate terminal of the charge transfer gate.