Closed loop lane synchronization for optical modulation

Abstract

A system for transmitting signals via serial links includes a plurality of lanes for combining data onto a transmission media, a skew detector configured to detect skew among two of the plurality of lanes, and a variable delay circuit controlled by the skew detector, configured to delay the start of a clock signal to circuitry of one of the plurality of lanes.

What is claimed is: 
     
       1. A system for transmitting signals via serial links, comprising:
 a plurality of lanes for combining data onto a transmission medium, comprising:
 a first lane comprising a first modulation driver signal and a second modulation driver signal; 
 a second lane comprising a first modulation driver signal and a second modulation driver signal; 
 
 a skew detector electrically coupled to a first output of a first modulation driver of said first lane of said plurality of lanes and electrically coupled to a second output of a second modulation driver of said second lane of said plurality of lanes configured to detect skew among said first lane and said second lane; and 
 a variable delay circuit controlled by said skew detector, configured to delay the start of a clock signal to circuitry of one of said plurality of lanes. 
 
     
     
       2. The system of  claim 1  wherein the variable delay circuit is configured to delay the clock signal to the circuitry of one of said plurality of lanes such that the skew between the lanes is adjusted. 
     
     
       3. The system of  claim 2  further comprising a test pattern generator configured to supply test patterns to said plurality of lanes to be used to detect said skew among two of said plurality of lanes. 
     
     
       4. The system of  claim 3  wherein said test patterns comprise at least two test patterns based on different numbers of symbols. 
     
     
       5. The system of  claim 4  wherein the at least two test patterns comprise different prime numbers of symbols. 
     
     
       6. The system of  claim 5  wherein the at least two test patterns comprise a least common multiple of their symbol numbers that is greater than an expected size of a skew in symbols. 
     
     
       7. The system of  claim 4  wherein the skew detector is configured to control a common reset signal for resetting the plurality of lanes and to assert said common reset signal if an unintended skew is detected between any pair of lanes. 
     
     
       8. A system for transmitting signals via serial links, comprising:
 a plurality of lanes for combining data onto a transmission medium, comprising:
 a first lane comprising a first modulation driver signal and a second modulation driver signal; 
 a second lane comprising a first modulation driver signal and a second modulation driver signal; and 
 
 a skew adjustment circuit configured to adjust skew between said first lane and said second lane of said plurality of lanes in a closed loop manner based on detecting skew between outputs of modulation drivers corresponding to said first modulation driver signal of said first lane and said second modulation driver signal of said second lane, 
 wherein the skew adjustment circuit comprises a variable delay circuit that delays a start of a clock signal to circuitry of a lane. 
 
     
     
       9. The system of  claim 8  wherein a skew detector is used to control the skew adjustment circuit and a common reset signal of the plurality of lanes. 
     
     
       10. The system of  claim 8  wherein the skew adjustment circuit is configured to introduce an intentional skew between two lanes. 
     
     
       11. The system of  claim 8  further comprising a plurality of said skew adjustment circuits, wherein skews between more than two lanes of said plurality of lanes are adjusted relative to each other by sequentially adjusting skew between all lanes, one pair at a time. 
     
     
       12. The system of  claim 8  wherein the skew adjustment circuit is configured to introduce intentional skews between multiple lanes. 
     
     
       13. The system of  claim 8  wherein a skew detector is used to control the skew adjustment circuit to adjust the start of a clock to one lane and assert a common reset signal of the plurality of lanes. 
     
     
       14. A system for transmitting signals via optical serial links, comprising:
 a plurality of lanes for combining independent data onto an optical transmission waveguide; and 
 a skew adjustment component for each of the plurality of lanes, configured to adjust skew of a respective lane responsive to an output of a skew detector, wherein the skew adjustment component comprises a variable delay circuit controlled by said skew detector, configured to delay a start of a clock signal to circuitry of one of said plurality of lanes, 
 wherein the skew detector is configured to detect skew among two adjacent lanes, and 
 wherein said skew detector is configured to sense outputs of modulation drivers corresponding to said two adjacent lanes. 
 
     
     
       15. The system of  claim 14  wherein the variable delay circuit is configured to delay the clock signal to circuitry of one of said plurality of lanes such that the skew between the lanes is adjusted. 
     
     
       16. The system of  claim 14  further comprising a test pattern generator configured to supply test patterns to said plurality of lanes to be used to detect said skew among said two adjacent lanes. 
     
     
       17. The system of  claim 16  wherein said test patterns comprise at least two test patterns based on different numbers of symbols. 
     
     
       18. The system of  claim 14  wherein the skew detector is configured to control a common reset signal for resetting the plurality of lanes and to assert said common reset signal if an unintended skew is detected between any pair of lanes. 
     
     
       19. The system of  claim 14  wherein the skew detector is used to control the skew adjustment component and a common reset signal of the plurality of lanes.