Systems and methods for break out of interconnections for high-density integrated circuit packages on a multi-layer printed circuit board

Abstract

A multi-layer printed circuit board having a first landing pad in a first layer and along a first axis arranged to receive a positive signal and a second landing pad in the first layer and along a second axis that is spaced away from the first axis longitudinally in the first layer and where the second landing pad arranged to receive a negative signal. A first buried in a second layer and along the first axis is spaced away from the first landing pad along the first axis. A second buried in the second layer and along the second axis is spaced away from the second landing pad along the second axis. A first signal connector provides a first electrical connection between the first landing pad and the second buried via and a second signal connector provides a second electrical connection between the second landing pad and the first buried via.

What is claimed is: 
     
       1. A printed circuit board (PCB) including an integrated circuit comprising:
 a first landing pad being positioned in a first layer of the PCB and along a first axis extending to the integrated circuit, the first landing pad arranged to receive a positive signal; 
 a second landing pad being positioned in the first layer of the PCB and along a second axis extending to the integrated circuit, the second axis being spaced away from the first axis longitudinally in the first layer, the second landing pad arranged to receive a negative signal; 
 a first buried via being positioned in a second layer of the PCB and along the first axis extending to the integrated circuit, the first buried via being spaced away from the first landing pad along the first axis; 
 a second buried via being positioned in the second layer of the PCB and along the second axis extending to the integrated circuit, the second buried via being spaced away from the second landing pad along the second axis; 
 a first signal connector arranged to provide a first electrical connection between the first landing pad and the second buried via; and 
 a second signal connector arranged to provide a second electrical connection between the second landing pad and the first buried via. 
 
     
     
       2. The PCB of  claim 1 , wherein the first signal connector includes a first microvia with a first trace connected to the first landing pad and a second trace connected to second buried via. 
     
     
       3. The PCB of  claim 1 , wherein the second signal connector includes a second microvia with a third trace connected to the second landing pad and a fourth trace connected to the first buried via. 
     
     
       4. The PCB of  claim 1  comprising a third layer between the first layer and the second layer. 
     
     
       5. The PCB of  claim 4 , wherein the third layer forms a gap along the first axis between the first landing pad and the first buried via. 
     
     
       6. The PCB of  claim 4 , wherein the third layer forms a gap along the second axis between the second landing pad and the second buried via. 
     
     
       7. The PCB of  claim 1 , wherein the first buried via is in electrical communication with at least one additional via in an additional layer of the PCB. 
     
     
       8. The PCB of  claim 1 , wherein the second buried via is in electrical communication with at least one additional via in an additional layer of the PCB. 
     
     
       9. A method for manufacturing a printed circuit board (PCB) including an integrated circuit comprising:
 positioning a first landing pad in a first layer of the PCB and along a first axis extending toward the integrated circuit, the first landing pad arranged to receive a positive signal; 
 positioning a second landing pad in the first layer of the PCB and along a second axis extending to the integrated circuit, the second axis being spaced away from the first axis longitudinally in the first layer, the second landing pad arranged to receive a negative signal; 
 positioning a first buried via in a second layer of the PCB and along the first axis extending toward the integrated circuit, the first buried via being spaced away from the first landing pad along the first axis; 
 positioning a second buried via in the second layer of the PCB and along the second axis extending toward the integrated circuit, the second buried via being spaced away from the second landing pad along the second axis; 
 providing a first electrical connection using a first signal connector between the first landing pad and the second buried via; and 
 providing a second electrical connection using a second signal connector between the second landing pad and the first buried via. 
 
     
     
       10. The method of  claim 9 , wherein the first signal connector includes a first microvia with a first trace connected to the first landing pad and a second trace connected to second buried via. 
     
     
       11. The method of  claim 9 , wherein the second signal connector includes a second microvia with a third trace connected to the second landing pad and a fourth trace connected to the first buried via. 
     
     
       12. The method of  claim 9  comprising providing a third layer between the first layer and the second layer. 
     
     
       13. The method of  claim 12 , wherein the third layer forms a gap along the first axis between the first landing pad and the first buried via. 
     
     
       14. The method of  claim 12 , wherein the third layer forms a gap along the second axis between the second landing pad and the second buried via. 
     
     
       15. The method of  claim 9 , wherein the first buried via is in electrical communication with at least one additional via in an additional layer of the PCB. 
     
     
       16. The method of  claim 9 , wherein the second buried via is in electrical communication with at least one additional via in an additional layer of the PCB.