Loading data from memory during dispatch
Abstract
A dispatch element interfaces with a host processor and dispatches threads to one or more tiles of a hybrid threading fabric. Data structures in memory to be used by a tile may be identified by a starting address and a size, included as parameters provided by the host. The dispatch element sends a command to a memory interface to transfer the identified data to the tile that will use the data. Thus, when the tile begins processing the thread, the data is already available in local memory of the tile and does not need to be accessed from the memory controller. Data may be transferred by the dispatch element while the tile is performing operations for another thread, increasing the percentage of operations performed by the tile that are performing useful work and reducing the percentage that are merely retrieving data.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A system comprising:
a memory; and
a plurality of tiles coupled to the memory, each tile of the plurality of tiles comprising one or more processing elements; and
a dispatch interface block coupled to the memory and the plurality of tiles and configured to perform operations comprising:
receiving a dispatch request that comprises a first field that identifies a tile and a second field that identifies an address in the memory;
requesting, from the memory, that data at the address be transferred to the identified tile; and
in response to the received dispatch request, starting a thread on the identified tile.
2. The system of claim 1 , wherein:
the dispatch request is received from a host processor.
3. The system of claim 1 , wherein the requesting of the data from the memory comprises sending a data request to a memory controller chiplet that controls access to the memory.
4. The system of claim 1 , wherein:
the dispatch request further identifies a size of the data to be transferred; and
the request to the memory that the data be transferred identifies the size.
5. The system of claim 1 , wherein:
the dispatch request further identifies a number of messages that will send the data to the identified tile.
6. The system of claim 1 , wherein the dispatch request comprises a third field that identifies a width of the data.
7. The system of claim 1 , wherein the dispatch request further identifies that the data is to be replicated into all single-instruction/multiple-data (SIMD) lanes.
8. The system of claim 1 , wherein the dispatch request further identifies that the data is to be transferred to a base context of the identified tile instead of tile memory.
9. A non-transitory machine-readable medium that stores instructions that, when executed by a host interface and dispatch module coupled to a host and a tile of a hybrid threading fabric, cause the host interface and dispatch module to perform operations comprising:
receiving, from the host, a dispatch request that comprises a first field that identifies a tile and a second field that identifies an address in a memory;
requesting, from the memory, that data at the address be transferred to the identified tile; and
in response to the received dispatch request, starting a thread on the identified tile.
10. The non-transitory machine-readable medium of claim 9 , wherein the requesting of the data from the memory comprises sending a data request to a memory controller chiplet that controls access to the memory.
11. The non-transitory machine-readable medium of claim 9 , wherein:
the dispatch request further identifies a size of the data to be transferred; and
the request to the memory that the data be transferred identifies the size.
12. The non-transitory machine-readable medium of claim 9 , wherein:
the dispatch request further identifies a number of messages that will send the data to the identified tile.
13. The non-transitory machine-readable medium of claim 9 , wherein the dispatch request comprises a third field that identifies a width of the data.
14. The non-transitory machine-readable medium of claim 9 , wherein the dispatch request further identifies that the data is to be replicated into all single-instruction/multiple-data (SIMD) lanes.
15. The non-transitory machine-readable medium of claim 9 , wherein the dispatch request further identifies that the data is to be transferred to a base context of the tile instead of tile memory.
16. A method comprising:
receiving a dispatch request that comprises a first field that identifies a tile and a second field that identifies an address in a memory;
requesting, from the memory, that data at the address be transferred to the identified tile; and
in response to the received dispatch request, starting a thread on the identified tile.
17. The method of claim 16 , wherein:
the dispatch request is received from a host processor.
18. The method of claim 16 , wherein the requesting of the data from the memory comprises sending a data request to a memory controller chiplet that controls access to the memory.
19. The method of claim 16 , wherein:
the dispatch request further identifies a size of the data to be transferred; and
the request to the memory that the data be transferred identifies the size.
20. The method of claim 16 , wherein:
the dispatch request further identifies a number of messages that will send the data to the identified tile.
21. The method of claim 16 , wherein the dispatch request comprises a third field that identifies a width of the data.
22. The method of claim 16 , wherein the dispatch request further identifies that the data is to be replicated into all single-instruction/multiple-data (SIMD) lanes.
23. The method of claim 16 , wherein the dispatch request further identifies that the data is to be transferred to a base context of the tile instead of tile memory.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.