Wideband amplifier linearization techniques

Abstract

A wideband power amplifier (PA) linearization technique is proposed. A current interpolation technique is proposed to linearize power amplifiers over a wide bandwidth. The wideband power amplifier linearization technique employs a novel transconductance Gm linearizer using a current interpolation technique that achieves improvement in the third order intermodulation over wide bandwidth for a sub-micron CMOS differential power amplifier. By using a small amount of compensating bias into an opposite phase differential pair, linearization over wide bandwidth is achieved and can be optimized by adjusting the compensating bias.

What is claimed is: 
     
       1. A linearized differential power amplifier (PA), comprising:
 a first differential transistor pair of MN 1  and MN 2 , wherein MN 1  gate and MN 2  gate are coupled to an input node, and MN 1  drain and MN 2  drain are positive-coupled to an output node; 
 a second differential transistor pair of MN 3  and MN 4 , wherein MN 3  gate and MN 4  gate are coupled to the input node, and MN 3  drain and MN 4  drain are negative-coupled to the output node; 
 a first normal tail biasing transistor MB 1  for supplying an operating bias current to the first differential transistor pair; and 
 a second compensating tail biasing transistor MB 2  for supplying a compensating bias current to the second differential transistor pair, wherein the compensating bias current is to be subtracted from the operating bias current to achieve linearization of the PA. 
 
     
     
       2. The PA of  claim 1 , wherein MB 1  has a small channel resistance such that the operating bias current of the first differential transistor pair is higher than the compensating bias current. 
     
     
       3. The PA of  claim 1 , wherein MB 2  has a large channel resistance such that the compensating bias current of the second differential transistor pair is lower than the operating bias current. 
     
     
       4. The PA of  claim 1 , wherein the first differential transistor pair of MN 1  and MN 2  generates a positive gain of +Δ/2 for the PA. 
     
     
       5. The PA of  claim 1 , wherein the second differential transistor pair of MN 3  and MN 4  generates a negative gain of −Δ/2 for the PA. 
     
     
       6. The PA of  claim 1 , further comprising:
 a third normal tail biasing transistor MB 3  for supplying a second operating bias current to the second differential transistor pair; and 
 a fourth compensating tail biasing transistor MB 4  for supplying a second compensating bias current to the first differential transistor pair, wherein the second compensating bias current is to be subtracted from the second operating bias current to achieve linearization of the PA. 
 
     
     
       7. The PA of  claim 6 , wherein MB 3  has a small channel resistance and MB 4  has a large channel resistance such that the second operating bias current is higher than the second compensating bias current. 
     
     
       8. The PA of  claim 6 , wherein a control signal turns on MB 1  and MB 2  and turns off MB 3  and MB 4  for a positive power gain +Δ/2 of the PA, and wherein a control signal turns off MB 1  and MB 2  and turns on MB 3  and MB 4  for a negative power gain −Δ/2 of the PA. 
     
     
       9. The PA of  claim 1 , further comprising:
 an input matching network coupled to the input node for receiving input signals; and 
 an output matching network coupled to the output node for generating amplified output signals. 
 
     
     
       10. The PA of  claim 1 , wherein the linearized PA has a reduced third order intermodulation (IM 3 ) over a wide bandwidth. 
     
     
       11. A method performed by a linearized power amplifier (PA), comprising:
 receiving an input signal by a first differential transistor pair of MN 1  and MN 2 , wherein MN 1  gate and MN 2  gate are coupled to an input node, and MN 1  drain and MN 2  drain are positive-coupled to an output node; 
 receiving the input signal by a second differential transistor pair of MN 3  and MN 4 , wherein MN 3  gate and MN 4  gate are coupled to the input node, and MN 3  drain and MN 4  drain are negative-coupled to the output node; 
 supplying an operating bias current to the first differential transistor pair by a first normal tail biasing transistor MB 1 ; and 
 supplying a compensating bias current to the second differential transistor pair by a second compensating tail biasing transistors transistor MB 2 , wherein the compensating bias current is to be subtracted from the operating bias current to achieve linearization of the PA. 
 
     
     
       12. The method of  claim 11 , wherein MB 1  has a small channel resistance such that the operating bias current of the first differential transistor pair is higher than the compensating bias current. 
     
     
       13. The method of  claim 11 , wherein MB 2  has a large channel resistance such that the compensating bias current of the second differential transistor pair is lower than the operating bias current. 
     
     
       14. The method of  claim 11 , wherein the first differential transistor pair of MN 1  and MN 2  generates a positive gain of +Δ/2 for the input signals. 
     
     
       15. The method of  claim 11 , wherein the second differential transistor pair of MN 3  and MN 4  generates a negative gain of −Δ/2 for the input signals. 
     
     
       16. The method of  claim 11 , further comprising:
 supplying a second operating bias current to the second differential transistor pair by a third normal tail biasing transistor MB 3 ; and 
 supplying a second compensating bias current to the first differential transistor pair by a fourth compensating tail biasing transistor MB 4 , wherein the second compensating bias current is to be subtracted from the second operating bias current to achieve linearization of the PA. 
 
     
     
       17. The method of  claim 16 , wherein MB 3  has a small channel resistance and MB 4  has a large channel resistance such that the second operating bias current is higher than the second compensating bias current. 
     
     
       18. The method of  claim 16 , wherein a control signal turns on MB 1  and MB 2  and turns off MB 3  and MB 4  for a positive power gain +Δ/2 of the PA, and wherein a control signal turns off MB 1  and MB 2  and turns on MB 3  and MB 4  for a negative power gain −Δ/2 of the PA. 
     
     
       19. The method of  claim 11 , wherein the input signal is received onto an input matching network (IMN), and wherein an output signal is generated from an output matching network (OMN). 
     
     
       20. The method of  claim 11 , wherein the linearized PA has a reduced third order intermodulation (IM 3 ) over a wide bandwidth.