Flip flop circuit

Abstract

A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.

What is claimed is: 
     
       1. A pulse-based flip flop circuit, comprising:
 a pulse generator circuit configured to generate a pulse signal and an inverted pulse signal; 
 a scan hold buffer configured to hold a scan input signal for a delay time; and 
 a latch circuit including an intermediate node receiving one of a data signal and the scan input signal provided by the scan hold buffer in response to a scan enable signal, 
 wherein the pulse generator circuit comprises 
 an input node, 
 a direct path providing a clock signal as a direct path input to a NAND circuit, 
 a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and 
 a feedback path providing the pulse signal to a first stage among the number of stages of the delay path, and 
 wherein the first stage receives the clock signal and inverts the clock signal to provide an inverted clock signal, and the first stage includes a first N-type transistor connected between the input node and ground, and 
 a gate of the first N-type transistor receives the pulse signal via the feedback path. 
 
     
     
       2. The pulse-based flip flop circuit of  claim 1 , wherein the number of stages of the delay path is an odd number greater than 2. 
     
     
       3. The pulse-based flip flop circuit of  claim 1 , wherein the first stage further includes a second N-type transistor connected between the first stage and ground, and
 a gate of the second N-type transistor is connected to an input of a last stage among the number of stages of the delay path. 
 
     
     
       4. The pulse-based flip flop circuit of  claim 1 , wherein the latch circuit comprises:
 an input unit configured to provide the one of the data signal and the scan input signal provided by the scan hold buffer to the intermediate node as an intermediate signal in response to the scan enable signal; and 
 a latch unit configured to latch the intermediate signal as an output signal of the pulse-based flip flop circuit in response to the pulse signal and the inverted pulse signal. 
 
     
     
       5. The pulse-based flip flop circuit of  claim 4 , wherein the input unit of the latch circuit comprises:
 an inverter circuit inverting the scan enable signal to provide an inverted scan enable signal; 
 a first tri-state inverter inverting the scan input signal provided by the scan hold buffer to provide an inverted scan input signal in response to the inverted scan enable signal and the scan enable signal; and 
 a second tri-state inverter inverting the data signal to provide an inverted data signal in response to the inverted scan enable signal and the scan enable signal. 
 
     
     
       6. The pulse-based flip flop circuit of  claim 5 , wherein the latch unit of the latch circuit comprises:
 an output driver driving the output signal of the pulse-based flip flop circuit; 
 a third tri-state inverter providing the intermediate signal to a latch node as a latch signal in response to the pulse signal and the inverted pulse signal; 
 an inverter inverting the latch signal to provide an inverted latch signal; and 
 a fourth tri-state inverter inverting the inverted latch signal to provide the latch signal to an input of the output driver in response to the pulse signal and the inverted pulse signal. 
 
     
     
       7. The pulse-based flip flop circuit of  claim 1 , wherein, the scan hold buffer includes at least a first scan hold buffer circuit and a second scan hold buffer circuit,
 the latch circuit includes at least a first latch circuit connected to the first scan hold buffer circuit and a second latch circuit connected to the second scan hold buffer circuit, and 
 an output signal of the pulse-based flip flop circuit is a multi-bit signal. 
 
     
     
       8. The pulse-based flip flop circuit of  claim 1 , wherein the first stage further comprises:
 a second N-type transistor connected between the first stage and ground and having a gate connected to an input of a last stage among the number of stages of the delay path; 
 a first P-type transistor connected to the input node and having a gate that receives the clock signal; 
 a first N-type reset transistor connected between the input node and ground and having a gate that receives a reset signal; and 
 a first P-type reset transistor connected between the first P-type transistor and a power supply voltage and having a gate that receives the reset signal. 
 
     
     
       9. The pulse-based flip flop circuit of  claim 8 , wherein the latch circuit comprises:
 an input unit configured to provide the one of the data signal and the scan input signal provided by the scan hold buffer to the intermediate node as an intermediate signal in response to the scan enable signal; and 
 a latch unit configured to latch the intermediate signal as an output signal of the pulse-based flip flop circuit in response to the pulse signal and the inverted pulse signal, and reset the output signal in response to the reset signal. 
 
     
     
       10. A pulse generator circuit configured to provide a pulse signal to a latch circuit of a pulse-based flip flop circuit, the pulse generator circuit comprising:
 a direct path receiving a clock signal and providing the clock signal as a direct path input to a NAND circuit; 
 a delay path receiving the clock signal and including an odd number of series-connected stages including at least a first stage, an intermediate stage, and a last stage; 
 a feedback path providing the pulse signal as a first feedback signal to the first stage; and 
 an inverter inverting an inverted pulse signal to provide the pulse signal, 
 wherein the series-connected stages delay the clock signal to provide a delay path input to the NAND circuit, and the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, 
 wherein the first stage comprises 
 an input node, 
 a first N-type transistor connected between the input node and ground and having a gate that receives the first feedback signal, and 
 a second N-type transistor connected between the first stage and ground and having a gate that receives an input signal applied to the last stage as a second feedback signal. 
 
     
     
       11. The pulse generator circuit of  claim 10 , wherein the first stage receives the clock signal and inverts the clock signal to provide an inverted clock signal. 
     
     
       12. The pulse generator circuit of  claim 11 , further comprising:
 a NOR circuit that receives the delay path input and a reset signal and provides a reset version of the delay path input to the NAND circuit, and 
 the first stage further comprises 
 a first P-type transistor connected to the input node and having a gate that receives the clock signal, 
 a first N-type reset transistor connected between the input node and ground and having a gate that receives a reset signal, and 
 a first P-type reset transistor connected between the first P-type transistor and a power supply voltage and having a gate that receives the reset signal. 
 
     
     
       13. The pulse generator circuit of  claim 10 , wherein the delay path provides the clock signal as the delay path input to the NAND circuit through a NOR circuit. 
     
     
       14. A pulse-based multi-bit flip flop circuit, comprising:
 a first pair of adjacent metal lines including a first metal line and a second metal line bounding a first row extending in a first horizontal direction; 
 a second pair of adjacent metal lines including the second metal line and a third metal line bounding a second row extending in the first horizontal direction, wherein the second row is adjacent to the first row in a second horizontal direction that intersects the first horizontal direction; 
 a first divisional pulse generator, a first latch circuit, and a first scan hold buffer arranged in the first horizontal direction in the first row; and 
 a second divisional pulse generator, a second latch circuit, and a second scan hold buffer arranged in the first horizontal direction in the second row, 
 wherein an output of the first latch circuit is connected to an input of the second scan hold buffer. 
 
     
     
       15. The pulse-based multi-bit flip flop circuit of  claim 14 , wherein each of the first divisional pulse generator and the second divisional pulse generator comprises:
 a direct path receiving a clock signal and providing the clock signal as a direct path input to a NAND circuit; 
 a delay path receiving the clock signal and including series-connected stages including at least a first stage and a last stage; 
 an inverter receiving an inverted pulse signal and generating a pulse signal; and 
 a feedback path providing the pulse signal as a feedback signal to the first stage, 
 wherein the series-connected stages delay the clock signal to provide a delay path input to the NAND circuit, and the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal. 
 
     
     
       16. The pulse-based multi-bit flip flop circuit of  claim 15 , wherein the first divisional pulse generator and the second divisional pulse generator are arranged in alignment in the second horizontal direction;
 the first latch circuit and the second latch circuit are arranged in alignment in the second horizontal direction; and 
 the first scan hold buffer and the second scan hold buffer are arranged in alignment in the second horizontal direction. 
 
     
     
       17. The pulse-based multi-bit flip flop circuit of  claim 16 , wherein the first divisional pulse generator and the second divisional pulse generator are arranged in a first columnar region and operate in accordance with a first threshold voltage;
 the first latch circuit and the second latch circuit are arranged in a second columnar region and operate in accordance with a second threshold voltage; and 
 the first scan hold buffer and the second scan hold buffer are arranged in a third columnar region and operate in accordance with a third threshold voltage. 
 
     
     
       18. The pulse-based multi-bit flip flop circuit of  claim 17 , wherein one of the first threshold voltage, the second threshold voltage, and the third threshold voltage is different from another one of the first threshold voltage, the second threshold voltage, and the third threshold voltage.