Solid-state memory with intelligent cell calibration

Abstract

A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.

What is claimed is: 
     
       1. An apparatus comprising:
 a solid-state memory comprising non-individually erasable memory cells; 
 a grouping circuit configured to arrange the memory cells into calibration groups, each memory cell in each respective calibration group using a common set of read voltages to sense programmed states of the respective memory cells; and 
 a tracking circuit configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group; 
 the grouping circuit further configured to reassign a set of memory cells comprising less than all of the memory cells of a first calibration group into a different, second calibration group in response to the at least one measured read parameter, the reassigned set of memory cells in the second group retaining the programmed states thereof without an intervening garbage collection operation upon the reassigned set of memory cells. 
 
     
     
       2. The apparatus of  claim 1 , further comprising a calibration circuit configured to establish a first set of read voltages for use during read operations upon the memory cells in the first calibration group to determine the programmed states thereof and a different, second set of read voltages for use during read operations upon the memory cells in the second calibration group to determine the programmed states thereof. 
     
     
       3. The apparatus of  claim 2 , wherein the programmed states of the reassigned set of memory cells are sensed using both the first set of read voltages and the second set of read voltages without an intervening data refresh operation upon the reassigned set of memory cells. 
     
     
       4. The apparatus of  claim 1 , wherein the at least one read parameter comprises a detected read error rate obtained during a read operation upon the reassigned set of memory cells, and wherein the grouping circuit reassigns the set of memory cells from the first calibration group to the second calibration group responsive to the detected read error rate exceeding a predetermined threshold. 
     
     
       5. The apparatus of  claim 1 , further comprising an offset circuit configured to, responsive to the at least one read parameter obtained by the tracking circuit, apply an offset to the set of read voltages associated with a selected calibration group during a subsequent read operation upon selected memory cells within the selected calibration group. 
     
     
       6. The apparatus of  claim 1 , further comprising a granularity circuit configured to evaluate at least a selected one of data access metrics being tracked, sizes of cell calibration groups, and physical locations of cells in each calibration group, wherein the grouping circuit is further configured to rearrange the calibration groups responsive to the granularity circuit. 
     
     
       7. The apparatus of  claim 1 , wherein the second calibration group is a new calibration group made up of memory cells from the solid-state memory having similar data access performance characteristics. 
     
     
       8. The apparatus of  claim 1 , further comprising a monitor module controller configured to schedule a calibration sequence during which a calibration circuit establishes an updated set of read voltages for a third calibration group responsive to the at least one read parameter determined by the tracking circuit for the third calibration group exceeding a predetermined threshold. 
     
     
       9. The apparatus of  claim 8 , wherein the monitor module controller is further configured to cancel a previously scheduled calibration sequence for a fourth calibration group responsive to the at least one read parameter determined by the tracking circuit for the fourth calibration group not exceeding the predetermined threshold. 
     
     
       10. The apparatus of  claim 1 , wherein the solid-state memory comprises a flash memory arranged as a plurality of dies, wherein the memory cells are flash memory cells arranged on the plurality of dies, wherein the memory cells are each configured to store multiple bits as the associated programmed states, wherein the sets of read voltages for each of the calibration groups comprises different reference voltage levels to differentiate the respective multiple bits, wherein the memory cells are further arranged into garbage collection units (GCUs) that are respectively allocated and erased as a unit, and wherein the calibration groups are selected independently of the GCUs so that a selected GCU has memory cells in multiple calibration groups and a selected calibration group has memory cells in multiple GCUs. 
     
     
       11. A method comprising:
 arranging a plurality of non-individually erasable memory cells into calibration groups; 
 performing a calibration operation to determine an associated, set of reference voltages to sense programmed states of the respective memory cells in each calibration group; 
 measuring at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group using the associated set of reference voltages; 
 reassigning a set of memory cells comprising less than all of the memory cells of a first calibration group into a different, second calibration group in response to the at least one measured read parameter while retaining the programmed states of the reassigned set of memory cells therein; and 
 subsequently reading the current programmed states of the reassigned set of memory cells in the second group using the associated set of reference voltages for the second calibration group. 
 
     
     
       12. The method of  claim 11 , wherein the performing a calibration operation writes, and subsequently reads, test data to at least one memory cell of a selected calibration group to determine a new set of reference voltages. 
     
     
       13. The method of  claim 11 , wherein the performing a calibration operation establishes a first set of reference voltages for use during read operations upon the memory cells in the first calibration group to determine the programmed states thereof and a different, second set of reference voltages for use during read operations upon the memory cells in the second calibration group to determine the programmed states thereof, and wherein the programmed states of the reassigned set of memory cells are sensed using both the first set of read voltages and the second set of read voltages without an intervening garbage collection operation upon the reassigned set of memory cells. 
     
     
       14. The method of  claim 11 , wherein the performing a calibration operation alters a reference voltage without writing or reading data to any memory cells of a calibration group by using an offset value added to the reference voltage. 
     
     
       15. The method of  claim 11 , wherein the at least one read parameter comprises a detected read error rate obtained during a read operation upon the reassigned set of memory cells, and wherein the reassigned set of memory cells are transitioned from the first calibration group to the second calibration group responsive to the detected read error rate exceeding a predetermined threshold. 
     
     
       16. The method of  claim 11 , wherein the performing a calibration operation is carried out in response to an identification of at least one memory cell of a calibration group being at high risk for failure. 
     
     
       17. The method of  claim 11 , further comprising rearranging the calibration groups responsive to at least a selected one of data access metrics being tracked, sizes of cell calibration groups, and physical locations of cells in each calibration group. 
     
     
       18. The method of  claim 11 , wherein the performing a calibration operation comprises establishing an updated set of reference voltages for a third calibration group responsive to the at least one read parameter determined for the third calibration group exceeding a predetermined threshold. 
     
     
       19. The method of  claim 18 , wherein a previously scheduled calibration sequence for a fourth calibration group is cancelled responsive to the at least one read parameter determined by the tracking circuit for the fourth calibration group not exceeding the predetermined threshold. 
     
     
       20. The method of  claim 11 , wherein the performing a calibration operation executes multiple different calibration procedures sequentially in response to a changing volume of data access requests to the plurality of non-individually erasable memory cells.