Integrated circuit of a buck-boost converter with output current sensing function

Abstract

An integrated circuit of a buck-boost converter working in a buck mode with a buck power switching cycle, a boost mode with a boost power switching cycle or a buck-boost mode with a buck-boost power switching cycle. The integrated circuit integrates a first power switch, a second power switch, a third power switch and a fourth power switch, and an output current sensing circuit. The buck-boost power switching cycle consists of a first buck-boost phase, a second buck-boost phase and a third buck-boost phase. The output current sensing circuit samples the current flowing through the first power switch during the second buck-boost phase and the current flowing through the fourth power switch during the third buck-boost phase so as to generate the output current information.

What is claimed is: 
     
       1. An integrated circuit of a buck-boost converter, wherein the buck-boost converter has an inductor externally coupled to the integrated circuit and the inductor has a first terminal and a second terminal, and the buck-boost converter operates in a buck mode with a buck power switching cycle, a boost mode with a boost power switching cycle or a buck-boost mode with a buck-boost power switching cycle, the integrated circuit comprising:
 an input pin, a reference ground pin, a first power switching pin, a second power switching pin and an output pin, wherein the first power switching pin is coupled to the first terminal of the inductor and the second power switching pin is coupled to the second terminal of the inductor; 
 a first power switch, a second power switch, a third power switch and a fourth power switch, wherein the first power switch and the second power switch are coupled in series between the input pin and the reference ground pin and form a first common node coupled to the first power switching pin, and the third power switch and the fourth power switch are coupled in series between the output pin and the reference ground pin and form a second common node coupled to the second power switching pin; and 
 an output current sensing circuit, comprising: 
 a first sampling circuit, configured to provide a first sampling current representing a current flowing through the first power switch; 
 a second sampling circuit, configured to provide a second sampling current representing a current flowing through the fourth power switch; and 
 a current processing circuit, configured to generate a third sampling current based on the first sampling current and the second sampling current, wherein the buck-boost power switching cycle consists of a first buck-boost phase, a second buck-boost phase and a third buck-boost phase, wherein during one buck-boost power switching cycle, each of the first buck-boost phase, the second buck-boost phase and the third buck-boost phase is not repeated, and wherein a time period corresponding to the complete buck-boost power switching cycle is the sum of a time period of the first buck-boost phase, a time period of the second buck-boost phase and a time period of the third buck-boost phase, and wherein the third sampling current equals to zero during the first buck-boost phase, equals to the first sampling current during the second buck-boost phase, and equals to the second sampling current during the third buck-boost phase; 
 wherein the first power switch, the second power switch, the third power switch and the fourth power switch and the output current sensing circuit are formed in the same semiconductor die. 
 
     
     
       2. The integrated circuit as claimed in  claim 1 , wherein the third sampling current equals to the second sampling current during the buck power switching cycle, and wherein the boost power switching cycle comprises a first boost phase and a second boost phase, and the third sampling current equals to zero during the first boost phase and equals to the first sampling current during the second boost phase. 
     
     
       3. The integrated circuit as claimed in  claim 2 , wherein the first buck-boost phase is a phase in the buck-boost mode when the first power switch and the third power switch are on and the second power switch and the fourth power switch are off, the second buck-boost phase is a phase in the buck-boost mode when the first power switch and the fourth power switch are on and the second power switch and the third power switch are off, the third buck-boost phase is a phase in the buck-boost mode when the second power switch and the fourth power switch are on and the first power switch and the third power switch are off, and wherein the first boost phase is a phase in the boost mode when the first power switch and the third power switch are on and the second power switch and the fourth power switch are off, and the second boost phase is a phase in the boost mode when the first power switch and the fourth power switch are on and the second power switch and the third power switch are off. 
     
     
       4. The integrated circuit as claimed in  claim 1 , wherein the first power switch and the second power switch are coupled in series between an input terminal and a reference ground and form a first common node, and the third power switch and the fourth power switch are coupled in series between an output terminal and the reference ground and form a second common node, and wherein the buck-boost converter further comprises the inductor coupled between the first common node and the second common node. 
     
     
       5. The integrated circuit as claimed in  claim 1 ,
 wherein the first sampling circuit comprises:
 a first transistor having a source, a drain and a gate, wherein the drain of the first transistor is coupled to a drain of the first power switch, and the gate of the first transistor is configured to receive a first driving signal for driving the first power switch; 
 a first sampling resistor having a first terminal and a second terminal, wherein the first terminal of the first sampling resistor is coupled to the source of the first transistor, and the second terminal of the first sampling resistor is coupled to a source of the first power switch; and 
 a first amplifying circuit configured to amplify a voltage across the first sampling resistor and to generate the first sampling current; and 
 
 wherein the second sampling circuit comprises:
 a second transistor having a source, a drain and a gate, wherein the drain of the second transistor is coupled to a drain of the second power switch, and the gate of the second transistor is configured to receive a second driving signal for driving the second power switch; 
 a second sampling resistor having a first terminal and a second terminal, wherein the first terminal of the second sampling resistor is coupled to the source of the second transistor, and the second terminal of the second sampling resistor is coupled to a source of the second power switch; and 
 a second amplifying circuit configured to amplify a voltage across the second sampling resistor and to generate the second sampling current. 
 
 
     
     
       6. The integrated circuit as claimed in  claim 1 , wherein the current processing circuit comprises:
 a mode selection circuit, configured to generate a buck mode enable signal, a boost mode enable signal and a buck-boost mode enable signal based on an input voltage and an output voltage of the buck-boost converter; 
 an enable signal generating circuit, configured to generate a first enable signal and a second enable signal based on a second driving signal for driving the second power switch and a third driving signal for driving the third power switch; 
 a third transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the third transistor is configured to receive the first sampling current, and the third terminal of the third transistor is configured to receive the boost mode enable signal; 
 a fourth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the third terminal of the fourth transistor is configured to receive a fourth driving signal for driving the fourth power switch; 
 a fifth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the fifth transistor is configured to receive the first sampling current, and the third terminal of the fifth transistor is configured to receive the buck-boost mode enable signal; 
 a sixth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor, and the third terminal of the sixth transistor is configured to receive the first enable signal; 
 a seventh transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the seventh transistor is configured to receive the second sampling current, and the third terminal of the seventh transistor is configured to receive the buck mode enable signal; 
 an eighth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the eighth transistor is configured to receive the second sampling current, and the third terminal of the eighth transistor is configured to receive the buck-boost mode enable signal; and 
 a ninth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the ninth transistor is coupled to the first terminal of the eighth transistor, and the third terminal of the ninth transistor is configured to receive the second enable signal, wherein the first terminal of the fourth transistor, the first terminal of the sixth transistor, the first terminal of the seventh transistor and the first terminal of the ninth transistor are coupled to a common point to provide the third sampling current. 
 
     
     
       7. The integrated circuit as claimed in  claim 6 , wherein the mode selection circuit comprises:
 a buck comparator having a first input terminal configured to receive the input voltage, a second input terminal configured to receive the product of the output voltage and a first threshold, and an output terminal configured to provide the buck mode enable signal, wherein the first threshold is a constant higher than 1; 
 a boost comparator having a first input terminal configured to receive the input voltage, a second input terminal configured to receive the product of the output voltage and a second threshold, and an output terminal configured to provide the boost mode enable signal, wherein the second threshold is a constant less than 1 and higher than 0; and 
 a NOR gate having a first input terminal configured to receive the buck mode enable signal, a second input terminal configured to receive the boost mode enable signal, and an output terminal to provide the buck-boost mode enable signal. 
 
     
     
       8. The integrated circuit as claimed in  claim 6 , wherein the enable signal generating circuit comprises:
 a first RS trigger, having a set terminal, a reset terminal and an output terminal, wherein the set terminal is configured to receive a falling edge of the third driving signal, the reset terminal is configured to receive a rising edge of the second driving signal; and 
 a second RS trigger, having a set terminal, a reset terminal and an output terminal, wherein the set terminal of the second RS trigger is configured to receive the rising edge of the second driving signal, and the reset terminal of the second RS trigger is configured to receive a rising edge of the third driving signal. 
 
     
     
       9. The integrated circuit as claimed in  claim 6 , further comprising:
 a capacitor, coupled to the current processing circuit to receive the third sampling current; and 
 an output resistor, coupled in parallel with the capacitor; 
 wherein the capacitor and the output resistor are configured to provide an average value of the third sampling current during one power switching cycle. 
 
     
     
       10. An output current sensing circuit applied in a buck-boost converter, wherein the buck-boost converter has a first power switch, a second power switch, a third power switch and a fourth power switch, and the buck-boost converter operates in a buck mode with a buck power switching cycle, a boost mode with a boost power switching cycle or a buck-boost mode with a buck-boost power switching cycle, the output current sensing circuit comprising:
 a first sampling circuit, configured to provide a first sampling current representing a current flowing through the first power switch; 
 a second sampling circuit, configured to provide a second sampling current representing a current flowing through the fourth power switch; and 
 a current processing circuit, configured to generate a third sampling current based on the first sampling current and the second sampling current, wherein the buck-boost power switching cycle consists of a first buck-boost phase, a second buck-boost phase and a third buck-boost phase, wherein during one buck-boost power switching cycle, each of the first buck-boost phase, the second buck-boost phase and the third buck-boost phase is not repeated, and wherein a time period corresponding to the complete buck-boost power switching cycle is the sum of a time period of the first buck-boost phase, a time period of the second buck-boost phase and a time period of the third buck-boost phase, and wherein the third sampling current equals to zero during the first buck-boost phase, equals to the first sampling current during the second buck-boost phase, and equals to the second sampling current during the third buck-boost phase. 
 
     
     
       11. The output current sensing circuit as claimed in  claim 10 , wherein the third sampling current equals to the second sampling current during the buck power switching cycle, and wherein the boost power switching cycle comprises a first boost phase and a second boost phase, and the third sampling current equals to zero during the first boost phase and equals to the first sampling current during the second boost phase. 
     
     
       12. The output current sensing circuit as claimed in  claim 11 , wherein the first buck-boost phase is a phase in the buck-boost mode when the first power switch and the third power switch are on and the second power switch and the fourth power switch are off, the second buck-boost phase is a phase in the buck-boost mode when the first power switch and the fourth power switch are on and the second power switch and the third power switch are off, the third buck-boost phase is a phase in the buck-boost mode when the second power switch and the fourth power switch are on and the first power switch and the third power switch are off, and wherein the first boost phase is a phase in the boost mode when the first power switch and the third power switch are on and the second power switch and the fourth power switch are off, and the second boost phase is a phase in the boost mode when the first power switch and the fourth power switch are on and the second power switch and the third power switch are off. 
     
     
       13. The output current sensing circuit as claimed in  claim 10 , wherein the first power switch and the second power switch are coupled in series between an input terminal and a reference ground and form a first common node, and the third power switch and the fourth power switch are coupled in series between an output terminal and the reference ground and form a second common node, and wherein the buck-boost converter further comprises an inductor coupled between the first common node and the second common node. 
     
     
       14. The output current sensing circuit as claimed in  claim 10 ,
 wherein the first sampling circuit comprises:
 a first transistor having a source, a drain and a gate, wherein the drain of the first transistor is coupled to a drain of the first power switch, and the gate of the first transistor is configured to receive a first driving signal for driving the first power switch; 
 a first sampling resistor having a first terminal and a second terminal, wherein the first terminal of the first sampling resistor is coupled to the source of the first transistor, and the second terminal of the first sampling resistor is coupled to a source of the first power switch; and 
 a first amplifying circuit configured to amplify a voltage across the first sampling resistor and to generate the first sampling current; and 
 
 wherein the second sampling circuit comprises:
 a second transistor having a source, a drain and a gate, wherein the drain of the second transistor is coupled to a drain of the second power switch, and the gate of the second transistor is configured to receive a second driving signal for driving the second power switch; 
 a second sampling resistor having a first terminal and a second terminal, wherein the first terminal of the second sampling resistor is coupled to the source of the second transistor, and the second terminal of the second sampling resistor is coupled to a source of the second power switch; and 
 a second amplifying circuit configured to amplify a voltage across the second sampling resistor and to generate the second sampling current. 
 
 
     
     
       15. The output current sensing circuit as claimed in  claim 10 , wherein the current processing circuit comprises:
 a mode selection circuit, configured to generate a buck mode enable signal, a boost mode enable signal and a buck-boost mode enable signal based on an input voltage and an output voltage of the buck-boost converter; 
 an enable signal generating circuit, configured to generate a first enable signal and a second enable signal based on a second driving signal for driving the second power switch and a third driving signal for driving the third power switch; 
 a third transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the third transistor is configured to receive the first sampling current, and the third terminal of the third transistor is configured to receive the boost mode enable signal; 
 a fourth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the third terminal of the fourth transistor is configured to receive a fourth driving signal for driving the fourth power switch; 
 a fifth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the fifth transistor is configured to receive the first sampling current, and the third terminal of the fifth transistor is configured to receive the buck-boost mode enable signal; 
 a sixth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor, and the third terminal of the sixth transistor is configured to receive the first enable signal; 
 a seventh transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the seventh transistor is configured to receive the second sampling current, and the third terminal of the seventh transistor is configured to receive the buck mode enable signal; 
 an eighth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the eighth transistor is configured to receive the second sampling current, and the third terminal of the eighth transistor is configured to receive the buck-boost mode enable signal; and 
 a ninth transistor, having a first terminal, a second terminal and a third terminal, wherein the second terminal of the ninth transistor is coupled to the first terminal of the eighth transistor, and the third terminal of the ninth transistor is configured to receive the second enable signal, wherein the first terminal of the fourth transistor, the first terminal of the sixth transistor, the first terminal of the seventh transistor and the first terminal of the ninth transistor are coupled to a common point to provide the third sampling current. 
 
     
     
       16. The output current sensing circuit as claimed in  claim 15 , wherein the mode selection circuit comprises:
 a buck comparator having a first input terminal configured to receive the input voltage, a second input terminal configured to receive the product of the output voltage and a first threshold, and an output terminal configured to provide the buck mode enable signal, wherein the first threshold is a constant higher than 1; 
 a boost comparator having a first input terminal configured to receive the input voltage, a second input terminal configured to receive the product of the output voltage and a second threshold, and an output terminal configured to provide the boost mode enable signal, wherein the second threshold is a constant less than 1 and higher than 0; and 
 a NOR gate having a first input terminal configured to receive the buck mode enable signal, a second input terminal configured to receive the boost mode enable signal, and an output terminal to provide the buck-boost mode enable signal. 
 
     
     
       17. The output current sensing circuit as claimed in  claim 15 , wherein the enable signal generating circuit comprises:
 a first RS trigger, having a set terminal, a reset terminal and an output terminal, wherein the set terminal is configured to receive a falling edge of the third driving signal, the reset terminal is configured to receive a rising edge of the second driving signal; and 
 a second RS trigger, having a set terminal, a reset terminal and an output terminal, wherein the set terminal of the second RS trigger is configured to receive the rising edge of the second driving signal, and the reset terminal of the second RS trigger is configured to receive a rising edge of the third driving signal. 
 
     
     
       18. The output current sensing circuit as claimed in  claim 15 , further comprising:
 a capacitor, coupled to the current processing circuit to receive the third sampling current; and 
 an output resistor, coupled in parallel with the capacitor; 
 wherein the capacitor and the output resistor are configured to provide an average value of the third sampling current during one power switching cycle. 
 
     
     
       19. An output current sensing method for sensing an output current information of a buck-boost converter, wherein the buck-boost converter has a first power switch, a second power switch, a third power switch and a fourth power switch, the buck-boost converter operates in a buck mode with a buck power switching cycle, a boost mode with a boost power switching cycle or a buck-boost mode with a buck-boost power switching cycle, the output current sensing method comprising:
 generating a first sampling current representing a current flowing through the first power switch; 
 generating a second sampling current representing a current flowing through the fourth power switch; 
 generating a third sampling current based on the first sampling current and the second sampling current; and 
 generating output current information based on the third sampling current; 
 wherein the buck-boost power switching cycle consists of a first buck-boost phase, a second buck-boost phase and a third buck-boost phase, wherein during one buck-boost power switching cycle, each of the first buck-boost phase, the second buck-boost phase and the third buck-boost phase is not repeated, and wherein a time period corresponding to the complete buck-boost power switching cycle is the sum of a time period of the first buck-boost phase, a time period of the second buck-boost phase and a time period of the third buck-boost phase, and the step of generating the third sampling current comprises sampling the first sampling current to generate the third sampling current during the second buck-boost phase and sampling the second sampling current to generate the third sampling current during the third buck-boost phase and the third sampling current equals to zero during the first buck-boost phase. 
 
     
     
       20. The output current sensing method as claimed in  claim 19 , wherein the third sampling current equals to zero during the first buck-boost phase, equals to the first sampling current during the second buck-boost phase, and equals to the second sampling current during the third buck-boost phase, the third sampling current equals to the second sampling current during the buck power switching cycle, and the boost power switching cycle comprises a first boost phase and a second boost phase, and the third sampling current equals to zero during the first boost phase and equals to the first sampling current during the second boost phase.