Logic cell structures and related methods

Abstract

A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

The invention claimed is: 
     
       1. A method of forming an integrated circuit structure, the method comprising:
 providing a logic cell structure comprising a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network comprises a plurality of transistor segments; 
 determining a delay associated with at least one of the first input node and the second input node; 
 connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay. 
 
     
     
       2. The method of  claim 1 , further comprising:
 determining whether the delay is timing-critical. 
 
     
     
       3. The method of  claim 1 , wherein each of the plurality of transistor segments is associated with a substantially identical current-driving capability. 
     
     
       4. The method of  claim 1 , wherein each of the plurality of transistor segments has a substantially identical width measured in CPP. 
     
     
       5. The method of  claim 1 , wherein the pulling network is a first pulling network and the reference voltage is a first reference voltage and the plurality of transistor segments are a first plurality of transistor segments, wherein the logic cell structure further comprises:
 a second pulling network connected to a second reference voltage and the output node, wherein the second pulling network comprises a second plurality of transistor segments. 
 
     
     
       6. The method of  claim 5 , wherein connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay comprises:
 connecting the first and second pluralities of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay. 
 
     
     
       7. The method of  claim 5 , wherein the first plurality of transistor segments are n-channel transistor segments and the second plurality of transistor segments are p-channel transistor segments. 
     
     
       8. The method of  claim 5 , wherein the first pulling network is a pull-down network and the second pulling network is a pull-up network. 
     
     
       9. The method of  claim 1 , wherein determining a delay associated with at least one of the first input node and the second input node comprises:
 determining an additional delay associated with an additional logic cell structure connected to the logic cell structure. 
 
     
     
       10. The method of  claim 1 , further comprising:
 fabricating the logic cell structure on a semiconductor wafer. 
 
     
     
       11. The method of  claim 10 , wherein fabricating the logic cell structure on a semiconductor wafer comprises:
 exposing the semiconductor wafer to a radiation that is patterned based at least in part on the logic cell structure. 
 
     
     
       12. A method of forming an integrated circuit structure, the method comprising:
 providing a logic cell structure comprising a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network comprises a plurality of transistor segments; 
 determining a delay associated with at least one of the first input node and the second input node; 
 determining whether the delay is timing-critical; and 
 in response to the determination that the delay is timing-critical, connecting the plurality of transistor segments to the first input node, the second input node and the output node such that the input node associated with the determined delay controls a higher amount of current-driving capability of the plurality of transistor segments than the other input node. 
 
     
     
       13. The method of  claim 12 , further comprising:
 in response to the determination that the delay is timing-critical, adding an additional transistor segment connected to the input node associated with the determined delay. 
 
     
     
       14. The method of  claim 12 , further comprising:
 in response to the determination that the delay is not timing-critical, removing a transistor segment connected to the input node associated with the determined delay from the plurality of the transistor segments. 
 
     
     
       15. The method of  claim 12 , wherein the logic cell structure is an AND gate, an OR gate, a NOR gate, a NAND gate, an XOR gate, or a flip-flop. 
     
     
       16. A non-transitory computer-readable storage medium comprising executable instructions that, when executed, causes a processor to perform a method comprising:
 providing a logic cell structure comprising a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network comprises a plurality of transistor segments; 
 determining a delay associated with at least one of the first input node and the second input node; and 
 connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay. 
 
     
     
       17. The non-transitory computer-readable storage medium of  claim 16 , wherein the plurality of transistor segments are field-effect transistors (FETs). 
     
     
       18. The non-transitory computer-readable storage medium of  claim 16 , the method further comprising:
 determining whether the delay is timing-critical. 
 
     
     
       19. The non-transitory computer-readable storage medium of  claim 16 , wherein each of the plurality of transistor segments is associated with a substantially identical current-driving capability. 
     
     
       20. The non-transitory computer-readable storage medium of  claim 16 , wherein determining a delay associated with at least one of the first input node and the second input node comprises:
 determining an additional delay associated with an additional logic cell structure connected to the logic cell structure.