Array substrate, digital x-ray detector including the same, and method for manufacturing the same

Abstract

A lower electrode of a PIN diode and a second protective layer covering the PIN diode are formed not using separate mask processes, but using the same mask process using the same mask, thereby reducing the number of mask processes and thus increasing process efficiency. Further, the lower electrode of the PIN diode is patterned and then the second protective film covering the PIN diode is patterned such that both the former patterning and the latter patterning are carried out using a single mask process, thereby reduce increase in defects due to foreign materials or stains.

What is claimed is: 
     
       1. A method for manufacturing an array substrate for a digital X-ray detector, the method comprising:
 providing a base substrate having an active area and a pad area; 
 forming a thin-film transistor on the base substrate and in the active area; 
 forming a first protective layer on the base substrate so as to cover the thin-film transistor; 
 forming a lower electrode film on the first protective layer; 
 forming a PIN (P-type/I-type/N-type semiconductors) layer and an upper electrode on the lower electrode film and in the active area; 
 forming a second protective film on the lower electrode film so as to cover the PIN layer and the upper electrode; and 
 patterning the second protective film to form a second protective layer, and patterning the lower electrode film to form a lower electrode in the active area after patterning the second protective film, 
 wherein the second protective film and the lower electrode film are patterned using the same mask process. 
 
     
     
       2. The method of  claim 1 , wherein the second protective layer is patterned into a pattern corresponding to the lower electrode in the active area. 
     
     
       3. The method of  claim 1 , wherein each of the lower electrode film and the second protective film are formed to cover an entire face of the base substrate. 
     
     
       4. The method of  claim 1 , wherein the second protective film is patterned using a mask having a predefined pattern, and, subsequently, the lower electrode film is patterned using the same mask as in the pattering process of the second protective film. 
     
     
       5. The method of  claim 4 , wherein the second protective film is patterned using dry etching, while the lower electrode film is patterned using wet etching. 
     
     
       6. The method of  claim 1 , wherein the method further comprises, prior to forming the first protective layer, forming a pad electrode on the base substrate and in the pad area. 
     
     
       7. The method of  claim 6 , wherein the thin-film transistor includes an active layer, a first electrode, a second electrode and a gate electrode,
 wherein the pad electrode, the first electrode, and the second electrode are formed using the same mask process. 
 
     
     
       8. The method of  claim 6 , wherein forming the lower electrode includes patterning the lower electrode film to form a pad connection electrode in the pad area. 
     
     
       9. The method of  claim 8 , wherein the lower electrode and the pad connection electrode are formed using the same mask process. 
     
     
       10. The method of  claim 8 , wherein the second protective layer is patterned to a pattern corresponding to the pad connection electrode in the pad area. 
     
     
       11. The method of  claim 8 , wherein the method further comprises, after forming the second protective layer and the lower electrode, forming a bias electrode and a pad contact electrode in the active area and the pad area, respectively,
 wherein the bias electrode and the pad contact electrode are formed using the same mask process. 
 
     
     
       12. The method of  claim 11 , wherein the method further comprises forming a pad protective electrode covering the pad contact electrode in the pad area. 
     
     
       13. An array substrate for a digital X-ray detector, the array substrate comprising:
 a base substrate having an active area and a pad area; 
 a thin-film transistor disposed on the base substrate and in the active area; 
 a first protective layer covering the thin-film transistor and disposed in the active area and the pad area; 
 a PIN diode electrically connected to the thin-film transistor and disposed on the first protective layer and in the active area; and 
 a second protective layer covering the PIN diode and disposed in the active area and the pad area, 
 wherein the second protective layer does not contact the first protective layer, 
 wherein the PIN diode includes a lower electrode, a PIN layer and an upper electrode, and 
 wherein the second protective layer is in contact with a part of the upper surface of the lower electrode and the second protective layer does not cover a side face of the lower electrode. 
 
     
     
       14. The array substrate of  claim 13 , wherein a side face of the lower electrode is inclined downwardly and outwardly,
 wherein a top end of the lower electrode is positioned inwardly of a bottom end of the second protective layer. 
 
     
     
       15. The array substrate of  claim 13 , further comprising a bias electrode electrically connected to the PIN diode and disposed on the second protective layer and in the active area,
 wherein the upper electrode is electrically connected to the bias electrode via a contact-hole formed in the second protective layer. 
 
     
     
       16. The array substrate of  claim 15 , wherein the thin-film transistor includes an active layer, a first electrode, a second electrode, and a gate electrode,
 wherein the array substrate further comprises: 
 a pad electrode disposed in the pad area, wherein the pad electrode, the first electrode and the second electrode constitute the same layer; 
 a pad connection electrode disposed in the pad area, wherein the pad connection electrode, and the lower electrode constitute the same layer; and 
 a pad contact electrode disposed in the pad area, wherein the pad contact electrode, and the bias electrode constitute the same layer. 
 
     
     
       17. The array substrate of  claim 16 , wherein the array substrate further comprises a pad protective electrode disposed in the pad area, wherein the pad protective electrode covers the pad contact electrode. 
     
     
       18. A digital X-ray detector comprising:
 an array substrate for the digital X-ray detector according to  claim 13 ; and 
 a scintillator layer disposed on the array substrate to cover an active area thereof.