Memory management unit for multi-threaded architecture

Abstract

An exemplary multi-threaded memory management system comprises a memory management unit (MMU) configured with a plurality of physical address (PA) output ports individually dedicated to a respective plurality of threads, wherein the MMU is configured to adjust scheduling of the plurality of threads based on the status of an item requested from a cache. The MMU may be configured to translate a virtual address (VA) input from an individual thread to a PA output on the respective PA output port. The cache may be a translation look-aside buffer. The item requested from the cache may be in transient status when a response is expected or valid status when the response is received. The MMU may signal a thread scheduler to run a thread when a requested item's status becomes valid, permitting stalling individual threads without blocking other threads that continue running using the PA output port dedicated to each thread.

What is claimed is: 
     
       1. An apparatus comprising:
 a memory management unit (MMU) configured with a plurality of physical address (PA) output ports individually dedicated to a respective plurality of threads; 
 each respective thread of the plurality of threads executing processor executable instructions fetched from a virtual address (VA) determined by a per-thread program counter (PC) dedicated to the respective thread; 
 wherein the MMU is configured to adjust scheduling of the plurality of threads based on a status of an item requested from a cache; 
 the MMU configured to adjust scheduling of the plurality of threads at least in part by signaling the thread scheduler to run or not run one or more threads of the plurality of threads based on a status of an item requested by the one or more thread from a multi-level translation look-aside buffer (TLB); 
 the status of the item being one of transient status, valid status, or invalid status. 
 
     
     
       2. The apparatus of  claim 1 , wherein the apparatus further comprises the MMU is configured to translate the virtual address (VA) input from an individual thread to the PA output on the respective PA output port. 
     
     
       3. The apparatus of  claim 1 , wherein the cache further comprises a translation look-aside buffer (TLB). 
     
     
       4. The apparatus of  claim 1 , wherein the item requested further comprises an instruction. 
     
     
       5. The apparatus of  claim 1 , wherein the item requested further comprises data. 
     
     
       6. The apparatus of  claim 1 , wherein the status of the item requested from the cache further comprises expecting a response comprising the item requested from the cache. 
     
     
       7. The apparatus of  claim 1 , wherein the status of the item requested from the cache further comprises receiving a response comprising the item requested from the cache. 
     
     
       8. The apparatus of  claim 1 , wherein adjust scheduling further comprises signal a thread scheduler. 
     
     
       9. The apparatus of  claim 8 , wherein adjust scheduling of the plurality of threads based on the status of the item requested from the cache further comprises: in response to determining at least one thread will stall waiting for an expected response comprising the item requested from the cache, signal the thread scheduler to permit the at least one thread to not run; and in response to receiving the response comprising the item requested from the cache for the at least one thread, signal the thread scheduler to permit the at least one thread to run. 
     
     
       10. An apparatus comprising:
 a memory management unit (MMU) configured with a plurality of physical address (PA) output ports, wherein each PA output port of the plurality of PA output ports is individually dedicated to one respective thread of a plurality of threads, and wherein each respective thread of the plurality of threads executes processor executable instructions fetched from a virtual address (VA) determined by a per-thread Program Counter (PC) dedicated to the respective thread; 
 a thread scheduler operably coupled with the MMU, wherein the thread scheduler is configured to govern execution scheduling of the plurality of threads based at least in part on round-robin scheduling, wherein the MMU is configured to adjust scheduling of the plurality of threads at least in part by signaling the thread scheduler to run or not run one or more thread of the plurality of threads based on a status of an item requested by the one or more thread from a multi-level translation look-aside buffer (TLB), and wherein the status of the item requested from the multi-level TLB by the one or more thread is one of transient status, valid status, or invalid status; and 
 a multiplexer configured to govern the plurality of PA output ports, wherein the PA output port dedicated to each thread not having an invalid or transient status for the requested item is enabled. 
 
     
     
       11. The apparatus of  claim 10 , wherein the apparatus further comprises the multi-level TLB is operably coupled with a page table walk (PTW) unit configured to locate the item requested in response to receiving request for the item as a result of a miss in at least one level of the multi-level TLB, and wherein the multi-level TLB is operably coupled with the plurality of PA output ports to provide at least one response comprising the requested item. 
     
     
       12. The apparatus of  claim 10 , wherein the MMU further comprises the multi-level TLB configured to retrievably store a plurality of TLB entries wherein each TLB entry of the plurality of TLB entries comprises a Virtual Address, Physical Address (VA-PA) pair, wherein the plurality of VA-PA pairs are indexed per thread in the multi-level TLB by a unique thread Id. 
     
     
       13. The apparatus of  claim 12 , wherein the apparatus further comprises the MMU is configured to use the thread Id associated with one or more thread to locate the TLB entry storing a VA-PA pair associated with the item requested by the one or more thread from the multi-level TLB. 
     
     
       14. The apparatus of  claim 10 , wherein the apparatus further comprises each PA output port of the plurality of PA output ports is configured with a transient bit operably coupled with logic designed to determine a digital value of the transient bit based on the status of the item requested from the multi-level TLB by the one or more thread. 
     
     
       15. The apparatus of  claim 10 , wherein the apparatus further comprises each PA output port of the plurality of PA output ports is configured with a valid bit operably coupled with logic designed to determine a digital value of the valid bit based on the status of the item requested from the multi-level TLB by the one or more thread. 
     
     
       16. The apparatus of  claim 10 , wherein the apparatus further comprises logic configured to signal the thread scheduler to permit the at least one thread to run or not run based on a digital value of a transient bit or a valid bit configured in the PA output port dedicated to the at least one thread. 
     
     
       17. An apparatus comprising:
 a memory management unit (MMU) configured with a plurality of physical address (PA) output ports, wherein each PA output port of the plurality of PA output ports is individually dedicated to one respective thread of a plurality of threads, and wherein each respective thread of the plurality of threads executes processor executable instructions fetched from a virtual address (VA) determined by a per-thread Program Counter (PC) dedicated to the respective thread; 
 a thread scheduler operably coupled with the MMU, wherein the thread scheduler is configured to govern execution scheduling of the plurality of threads based at least in part on round-robin scheduling, wherein the MMU is configured to adjust scheduling of the plurality of threads at least in part by signaling the thread scheduler to run or not run one or more thread of the plurality of threads based on a status of an item requested by the one or more thread from a multi-level translation look-aside buffer (TLB), wherein the status of the item requested from the multi-level TLB by the one or more thread is one of transient status, valid status, or invalid status, wherein the multi-level TLB is operably coupled with a page table walk (PTW) unit configured to locate the item requested in response to receiving a request for the item as a result of a miss in at least one level of the multi-level TLB, and wherein the multi-level TLB and the PTW unit are operably coupled with the plurality of PA output ports to provide a plurality of responses simultaneous within a predetermined time period, wherein the plurality of responses comprise a respective plurality of requested items, wherein each requested item was requested by an individual thread of the plurality of threads, and wherein each response of the plurality of responses is output to the PA output port dedicated to the individual thread; and 
 a multiplexer adapted with a number of inputs corresponding to the number of the plurality of threads, wherein the multiplexer is configured to govern the plurality of PA output ports, and wherein the PA output port dedicated to each thread not having an invalid or transient status for any requested item is enabled. 
 
     
     
       18. The apparatus of  claim 17 , wherein the apparatus further comprises a pipelined processor operably coupled with the MMU. 
     
     
       19. The apparatus of  claim 18 , wherein the pipelined processor further comprises a superscalar processor. 
     
     
       20. The apparatus of  claim 18 , wherein the pipelined processor further comprises a plurality of fetch stages, and wherein the status of the item requested from the multi-level TLB by the one or more thread is determined as a function of an item status output from at least two fetch stages of the plurality of fetch stages.