Wireless circuitry with self-calibrated harmonic rejection mixers

Abstract

An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.

What is claimed is: 
     
       1. Wireless circuitry comprising:
 a first mixer with a first input configured to receive a first signal, a second input coupled to an input path, and a first output coupled to an output path; 
 a second mixer with a third input configured to receive a second signal, a fourth input coupled to the input path, and a second output coupled to the output path; and 
 a switch coupled between the second input and the third input. 
 
     
     
       2. The wireless circuitry of  claim 1  wherein the second signal is phase-delayed with respect to the first signal. 
     
     
       3. The wireless circuitry of  claim 1 , wherein the wireless circuitry is configured to receive an input signal on the input path and is configured to produce an output signal on the output path, the output signal having a higher frequency than the input signal. 
     
     
       4. The wireless circuitry of  claim 3 , wherein the output signal comprises a radio-frequency signal. 
     
     
       5. The wireless circuitry of  claim 1  further comprising:
 a third mixer having a fifth input configured to receive a third signal, a sixth input coupled to the input path, and a third output coupled to the output path; and 
 an additional switch coupled between the fourth input and the fifth input. 
 
     
     
       6. The wireless circuitry of  claim 5 , wherein the second signal is phase-delayed with respect to the first signal and the third signal is phase-delayed with respect to the first signal and the second signal. 
     
     
       7. The wireless circuitry of  claim 1 , wherein the first input and the third input are coupled to a programmable delay line. 
     
     
       8. The wireless circuitry of  claim 7 , wherein the first input is coupled to a first delay cell in the programmable delay line and the second input is coupled to a second delay cell in the programmable delay line. 
     
     
       9. The wireless circuitry of  claim 1 , further comprising:
 an additional switch that couples the input path to the second input. 
 
     
     
       10. The wireless circuitry of  claim 9 , wherein the wireless circuitry is configured to generate an output signal on the output path while the additional switch is closed and while the switch between the second input and the third input is open. 
     
     
       11. The wireless circuitry of  claim 10 , wherein the wireless circuitry is configured to generate a direct current (DC) voltage on the output path while the switch between the second input and the third input is closed and while the additional switch is open. 
     
     
       12. The wireless circuitry of  claim 1 , wherein the output path comprises first and second differential output lines. 
     
     
       13. A non-transitory computer-readable storage medium storing one or more programs configured to be executed by at least one processor, the one or more programs including instructions that, when executed by the at least one processor, cause the at least one processor to:
 use a first mixer to mix a first signal with a second signal that is phase-delayed with respect to the first signal; 
 use a second mixer to mix the second signal with a third signal that is phase-delayed with respect to the second signal; and 
 use at least the first and second mixers to output a direct current (DC) voltage onto an output path based on the first signal and the second signal. 
 
     
     
       14. The non-transitory computer-readable storage medium of  claim 13 , further comprising instructions that, when executed by the at least one processor, cause the at least one processor to:
 adjust the first, second, and third signals based on the DC voltage on the output path. 
 
     
     
       15. The non-transitory computer-readable storage medium of  claim 13 , further comprising instructions that, when executed by the at least one processor, cause the at least one processor to:
 use an adjustable load coupled to the output path to amplify the DC voltage to generate an amplified DC voltage. 
 
     
     
       16. The non-transitory computer-readable storage medium of  claim 15 , further comprising instructions that, when executed by the at least one processor, cause the at least one processor to:
 use an analog-to-digital converter (ADC) coupled to the output path to generate a digital output based on the amplified DC voltage. 
 
     
     
       17. The non-transitory computer-readable storage medium of  claim 15 , wherein adjusting the first signal produces a first calibrated signal, adjusting the second signal produces a second calibrated signal, and adjusting the third signal produces a third calibrated signal, further comprising instructions that, when executed by the at least one processor, cause the at least one processor to:
 use the first mixer circuit to mix the first calibrated signal with an input signal; 
 use the second mixer circuit to mix the second calibrated signal with the input signal; 
 use the first and second mixer circuits to generate radio-frequency signals on the output path based on the input signal, the first calibrated signal, and the second calibrated signal; 
 signals; and 
 amplify the radio-frequency signals to produce amplified radio-frequency use an antenna to transmit the amplified radio-frequency signals. 
 
     
     
       18. Wireless circuitry comprising:
 a first path; 
 a second path; 
 a delay line configured to generate a set of signals; 
 mixers coupled between the first path and the second path, the mixers being configured to generate a radio-frequency signal on the second path based on an input on the first path and based on the set of signals generated by the delay line; and 
 an adjustable load coupled to the second path. 
 
     
     
       19. The wireless circuitry of  claim 18 , wherein the adjustable load comprises:
 an inductor coupled to the second path; 
 a first switch coupled in series between the inductor and a circuit node; 
 a power supply terminal; 
 a second switch coupled between the power supply terminal and the circuit mode; 
 a transistor coupled between the second path and the power supply terminal, the transistor having a gate terminal coupled to the circuit node; and 
 a resistor coupled between the inductor and the circuit node in parallel with the first switch. 
 
     
     
       20. The wireless circuitry of  claim 18 , wherein the wireless circuitry is operable in a first mode and in a second mode, the mixers are configured to output the radio-frequency signal on the second path in the first mode and are configured to output a direct-current (DC) voltage on the second path in the second mode; and
 an analog-to-digital converter (ADC) coupled to the second path, the ADC being configured to generate a digital output based on the DC voltage in the second mode, and the one or more processors being configured to adjust the set of signals produced by the delay line based on the digital output in the second mode. 
 
     
     
       21. A method of operating wireless circuitry, the method comprising:
 with a first mixer, mixing a first signal with a second signal that is phase-delayed with respect to the first signal; 
 with a second mixer, mixing the second signal with a third signal that is phase-delayed with respect to the second signal; and 
 with at least the first and second mixers, outputting a direct current (DC) voltage onto an output path. 
 
     
     
       22. The method of  claim 21 , further comprising:
 with one or more processors, adjusting the first, second, and third signals based on the DC voltage on the output path.