Technologies for execute only transactional memory

Abstract

Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

The invention claimed is: 
     
       1. A computing device comprising:
 processor circuitry coupled to a memory, the processor circuitry to execute a page mis handler in response to a page miss, wherein the processor circuitry includes an instruction translation lookaside buffer and a data translation lookaside buffer, 
 wherein the processor circuitry to execute the page miss handler to: (i) determine whether a first page size associated with an execute only transactional range matches a second page size associated with a first physical memory address by a page table of the computing device and (ii) generate a page size mismatch fault in response to a determination that the first page size associated with the execute only transactional range does not match the second page size associated with the physical memory address by the page table. 
 
     
     
       2. The computing device of  claim 1 , wherein the instruction translation lookaside buffer is populated with a virtual-to-physical address mapping in response to a determination that the first page size associated with the execute only transactional range matches the second page size associated with the first physical memory address by the page table, wherein the processor circuitry is further to execute a mapping change handler in response to a change in value of a last instruction translation lookaside buffer hit register,
 wherein the processor circuitry to execute the mapping change handler to:
 determine a second physical memory address, wherein second physical memory address comprises a last translation value of the instruction translation lookaside buffer; 
 determine whether the second physical memory address is within the execute only transaction range; 
 determine whether an offset part of the second physical memory address matches a predefined entry point offset in response to a determination that the second physical memory address is within the execute only transaction range; and 
 generate a fault in response to a determination that the offset part of the second physical memory address does not match the predefined entry point offset. 
 
 
     
     
       3. The computing device of  claim 1 , wherein the processor circuitry is further to execute a miss handler in response to an instruction translation lookaside buffer miss, wherein the processor circuitry to execute the miss handler to:
 determine whether the first physical memory address associated with the instruction translation lookaside buffer miss is within an execute only transaction range; 
 determine whether the first physical memory address associated with the instruction translation lookaside buffer miss is at an authorized entry point in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is within the execute only transaction range; and 
 generate a fault in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is not at an authorized entry point. 
 
     
     
       4. The computing device of  claim 3 , wherein the processor circuitry to execute the miss handler to record an execute only transaction index of a virtual-to-physical address mapping associated with the instruction translation lookaside buffer miss in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is at an authorized entry point. 
     
     
       5. A method comprising:
 executing, by a processor coupled to a memory of a computing device, a page miss handler in response to a page miss, the processor including an instruction translation lookaside buffer and a data translation lookaside buffer; 
 determining, by the processor, whether a first page size associated with an execute only transactional range matches a second page size associated with a first physical memory address by a page table of the computing device; and 
 generating, by the processor, a page size mismatch fault in response to a determination that the first page size associated with the execute only transactional range does not match the second page size associated with the physical memory address by the page table. 
 
     
     
       6. The method of  claim 5 , wherein the instruction translation lookaside buffer is populated with a virtual-to-physical address mapping in response to a determination that the first page size associated with the execute only transactional range matches the second page size associated with the first physical memory address by the page table,
 wherein the method further comprises: 
 executing, by the processor, a mapping change handler in response to a change in value of a last instruction translation lookaside buffer hit register, wherein:
 determining, by the processor, a second physical memory address, wherein second physical memory address comprises a last translation value of the instruction translation lookaside buffer; 
 determining, by the processor, whether the second physical memory address is within the execute only transaction range; 
 determining, by the processor, whether an offset part of the second physical memory address matches a predefined entry point offset in response to a determination that the second physical memory address is within the execute only transaction range; and 
 generating, by the processor, a fault in response to a determination that the offset part of the second physical memory address does not match the predefined entry point offset. 
 
 
     
     
       7. The method of  claim 5 , further comprising:
 executing, by the processor, a miss handler in response to an instruction translation lookaside buffer miss; 
 determining, by the processor, whether the first physical memory address associated with the instruction translation lookaside buffer miss is within an execute only transaction range; 
 determining, by the processor, whether the first physical memory address associated with the instruction translation lookaside buffer miss is at an authorized entry point in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is within the execute only transaction range; and 
 generating, by the processor, a fault in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is not at an authorized entry point. 
 
     
     
       8. The method of  claim 7 , further comprising recording, by the processor, an execute only transaction index of a virtual-to-physical address mapping associated with the instruction translation lookaside buffer miss in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is at an authorized entry point. 
     
     
       9. At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
 executing a page miss handler in response to a page miss, the computing device having a processor including an instruction translation lookaside buffer and a data translation lookaside buffer; 
 determining whether a first page size associated with an execute only transactional range matches a second page size associated with a first physical memory address by a page table of the computing device; and 
 generating, a page size mismatch fault in response to a determination that the first page size associated with the execute only transactional range does not match the second page size associated with the physical memory address by the page table. 
 
     
     
       10. The non-transitory computer-readable medium of  claim 9 , wherein the instruction translation lookaside buffer is populated with a virtual-to-physical address mapping in response to a determination that the first page size associated with the execute only transactional range matches the second page size associated with the first physical memory address by the page table,
 wherein the operations further comprise:
 executing a mapping change handler in response to a change in value of a last instruction translation lookaside buffer hit register; 
 determining a second physical memory address, wherein second physical memory address comprises a last translation value of the instruction translation lookaside buffer; 
 determining whether the second physical memory address is within the execute only transaction range; 
 determining whether an offset part of the second physical memory address matches a predefined entry point offset in response to a determination that the second physical memory address is within the execute only transaction range; and 
 generating a fault in response to a determination that the offset part of the second physical memory address does not match the predefined entry point offset. 
 
 
     
     
       11. The non-transitory computer-readable medium of  claim 9 , wherein the operations further comprise:
 executing a miss handler in response to an instruction translation lookaside buffer miss, wherein: 
 determining whether the first physical memory address associated with the instruction translation lookaside buffer miss is within an execute only transaction range; 
 determining whether the first physical memory address associated with the instruction translation lookaside buffer miss is at an authorized entry point in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is within the execute only transaction range; and 
 generating a fault in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is not at an authorized entry point. 
 
     
     
       12. The non-transitory computer-readable medium of  claim 11 , wherein the operations further comprise recording an execute only transaction index of a virtual-to-physical address mapping associated with the instruction translation lookaside buffer miss in response to a determination that the first physical memory address associated with the instruction translation lookaside buffer miss is at an authorized entry point.