Level shifting circuit and method

Abstract

An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

What is claimed is: 
     
       1. An integrated circuit (IC) comprising:
 a first power supply node configured to have a first power supply voltage level; 
 a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level; 
 an n-well containing:
 first and second PMOS transistors comprising first source/drain (S/D) terminals coupled to the first power supply node; and 
 third and fourth PMOS transistors comprising second S/D terminals coupled to the second power supply node; 
 
 a bias circuit comprising;
 the first PMOS transistor comprising a third S/D terminal coupled to the n-well, and a gate coupled to the second power supply node; and 
 the third PMOS transistor comprising a fourth S/D terminal coupled to the n-well, and a gate coupled to the first power supply node; and 
 
 a level shifter comprising the second and fourth PMOS transistors. 
 
     
     
       2. The IC of  claim 1 , wherein
 the first power supply voltage level is greater than the second power supply voltage level by a magnitude greater than a threshold voltage of the first PMOS transistor. 
 
     
     
       3. The IC of  claim 1 , wherein
 the second power supply voltage level is greater than the first power supply voltage level by a magnitude greater than a threshold voltage of the third PMOS transistor. 
 
     
     
       4. The IC of  claim 1 , wherein
 the first power supply node is coupled to a first power domain configured to operate in both a first power-on mode in which the first power supply node has the first power supply voltage level and a first power-down mode in which the first power supply node has a reference voltage level, and 
 the second power supply node is coupled to a second power domain configured to operate in both a second power-on mode in which the second power supply node has the second power supply voltage level and a second power-down mode in which the second power supply node has the reference voltage level. 
 
     
     
       5. The IC of  claim 1 , wherein
 the level shifter comprises an inverter comprising the second PMOS transistor and a first NMOS transistor coupled between the first power supply node and a reference voltage node configured to have a reference voltage level, and 
 the inverter is configured to receive an input signal. 
 
     
     
       6. The IC of  claim 5 , wherein
 the n-well contains a fifth PMOS transistor, 
 the level shifter comprises:
 the fourth PMOS transistor, a first output signal path, and a second NMOS transistor coupled in series between the second power supply node and the reference voltage node, wherein a gate of the second NMOS transistor is configured to receive an output of the inverter; and 
 the fifth PMOS transistor, a second output signal path, and a third NMOS transistor coupled in series between the second power supply node and the reference voltage node, wherein a gate of the third NMOS transistor is configured to receive the input signal, and 
 
 the first and second output signal paths are configured to output complementary signal components based on the input signal. 
 
     
     
       7. The IC of  claim 6 , wherein a bulk terminal of each of the first through third NMOS transistors is configured to have the reference voltage level. 
     
     
       8. An integrated circuit (IC) comprising:
 a first power supply node configured to have a first power supply voltage level; 
 a second power supply node configured to have a second power supply voltage level different from the first power supply voltage level; 
 a reference voltage node configured to have a reference voltage level; 
 an n-well containing:
 first through third PMOS transistors comprising first source/drain (S/D) terminals coupled to the first power supply node; and 
 fourth and fifth PMOS transistors comprising second S/D terminals coupled to the second power supply node; 
 
 a bias circuit comprising;
 the first PMOS transistor comprising a third S/D terminal coupled to the n-well, and a gate coupled to the second power supply node; 
 the second PMOS transistor coupled in series with a first NMOS transistor between the first power supply node and the reference voltage node; and 
 the fourth PMOS transistor comprising a fourth S/D terminal coupled to the n-well, and a gate coupled to a node between the second PMOS transistor and the first NMOS transistor; and 
 
 a level shifter comprising the third and fifth PMOS transistors. 
 
     
     
       9. The IC of  claim 8 , wherein
 a difference between the first and second power supply voltage levels has a magnitude less than that of a threshold voltage of one of the first through fifth PMOS transistors. 
 
     
     
       10. The IC of  claim 8 , wherein
 the first power supply node is coupled to a first power domain configured to operate in both a first power-on mode in which the first power supply node has the first power supply voltage level and a first power-down mode in which the first power supply node has the reference voltage level, and 
 the second power supply node is coupled to a second power domain configured to operate in both a second power-on mode in which the second power supply node has the second power supply voltage level and a second power-down mode in which the second power supply node has the reference voltage level. 
 
     
     
       11. The IC of  claim 8 , wherein
 the level shifter comprises an inverter comprising the third PMOS transistor and a second NMOS transistor coupled between the first power supply node and the reference voltage node, and 
 the inverter is configured to receive an input signal. 
 
     
     
       12. The IC of  claim 11 , wherein
 the n-well contains a sixth PMOS transistor, 
 the level shifter comprises:
 the fifth PMOS transistor, a first output signal path, and a third NMOS transistor coupled in series between the second power supply node and the reference voltage node, wherein a gate of the third NMOS transistor is configured to receive an output of the inverter; and 
 the sixth PMOS transistor, a second output signal path, and a fourth NMOS transistor coupled in series between the second power supply node and the reference voltage node, wherein a gate of the fourth NMOS transistor is configured to receive the input signal, and 
 
 the first and second output signal paths are configured to output complementary signal components based on the input signal. 
 
     
     
       13. The IC of  claim 8 , wherein
 the level shifter comprises an inverter comprising the fifth PMOS transistor and a second NMOS transistor coupled between the second power supply node and the reference voltage node, and 
 the inverter is configured to receive an input signal. 
 
     
     
       14. The IC of  claim 13 , wherein
 the n-well contains a sixth PMOS transistor, 
 the level shifter comprises:
 the third PMOS transistor, a first output signal path, and a third NMOS transistor coupled in series between the first power supply node and the reference voltage node, wherein a gate of the third NMOS transistor is configured to receive an output of the inverter; and 
 the sixth PMOS transistor, a second output signal path, and a fourth NMOS transistor coupled in series between the first power supply node and the reference voltage node, wherein a gate of the fourth NMOS transistor is configured to receive the input signal, and 
 
 the first and second output signal paths are configured to output complementary signal components based on the input signal. 
 
     
     
       15. An integrated circuit (IC) comprising:
 a first power supply node configured to have a first power supply voltage level; 
 a second power supply node configured to have a second power supply voltage level greater than the first power supply voltage level; 
 an n-well containing:
 first and second PMOS transistors comprising first source/drain (S/D) terminals coupled to the first power supply node; and 
 third through fifth PMOS transistors comprising second S/D terminals coupled to the second power supply node; 
 
 a bias circuit comprising;
 the first PMOS transistor comprising a third S/D terminal coupled to the n-well, and a gate coupled to the second power supply node; and 
 the third PMOS transistor comprising a fourth S/D terminal coupled to the n-well, and a gate coupled to the first power supply node; and 
 
 a level shifter comprising the second, fourth, and fifth PMOS transistors. 
 
     
     
       16. The IC of  claim 15 , wherein a bulk terminal of each of the first through fifth PMOS transistors is coupled to the n-well. 
     
     
       17. The IC of  claim 15 , wherein
 the fourth PMOS transistor comprises a fifth S/D terminal coupled to a gate of the fifth PMOS transistor, and 
 the fifth PMOS transistor comprises a sixth S/D terminal coupled to a gate of the fourth PMOS transistor. 
 
     
     
       18. The IC of  claim 17 , wherein
 the level shifter further comprises first through third NMOS transistors, 
 the second PMOS transistor and the first NMOS transistor are coupled in series between the first power supply node and a reference voltage node configured to have a reference voltage level, 
 the second NMOS transistor is coupled between the fifth S/D terminal and the reference voltage node and comprises a gate coupled to a node between the second PMOS transistor and the first NMOS transistor, and 
 the third NMOS transistor is coupled between the sixth S/D terminal and the reference voltage node and comprises a gate coupled to gates of each of the second PMOS transistor and the first NMOS transistor. 
 
     
     
       19. The IC of  claim 15 , wherein
 a difference between the second power supply voltage level and the first power supply voltage level is greater than a threshold voltage of the third PMOS transistor. 
 
     
     
       20. The IC of  claim 15 , wherein
 the first power supply node is configured to have the first power supply voltage level during a first power-on mode and to have a reference voltage level during a first power-down mode, and 
 the second power supply node is configured to have the second power supply voltage level during a second power-on mode and to have a reference voltage level during a second power-down mode.