Output buffer, data driver, and display device having the same

Abstract

An output buffer is disclosed that includes: a buffer circuit that outputs an output signal to an output terminal based on a first input signal provided to a first input terminal and a second input signal provided to a second input terminal; and a current supply circuit that is connected in parallel to the buffer circuit, and provides an auxiliary current to the output terminal based on the first input signal and the second input signal.

What is claimed is: 
     
       1. An output buffer applied to a display device, comprising:
 a buffer circuit configured to output an output signal to an output terminal based on a first input signal provided to a first input terminal and a second input signal provided to a second input terminal; and 
 a current supply circuit connected in parallel to the buffer circuit and configured to provide an auxiliary current to the output terminal based on the first input signal and the second input signal, 
 wherein the current supply circuit comprises: 
 a current source generator connected to the first input terminal and configured to generate a first current provided to a first current path or a second current provided to a second current path based on the first input signal and the second input signal; 
 a first current controller connected between the second input terminal and the current source generator and configured to control the first current based on a third current generated by the first current; 
 a second current controller connected between the second input terminal and the current source generator and configured to control the second current based on a fourth current generated by the second current; 
 a first current output configured to provide a value obtained by multiplying the first current by k times (where k is a positive real number) as the auxiliary current to the output terminal; and 
 a second current output configured to allow a value obtained by multiplying the second current by k times as the auxiliary current to flow from the output terminal to a ground. 
 
     
     
       2. The output buffer of  claim 1 , wherein the current source generator comprises:
 a first P-type transistor connected between a power line and the ground, the first P-type transistor including a gate electrode connected to a first node connected to the first input terminal; 
 a first N-type transistor connected in parallel to the first P-type transistor between the power line and the ground, the first N-type transistor including a gate electrode connected to the first node; 
 a second P-type transistor connected between the first N-type transistor and the ground to form the first current path, the second P-type transistor including a gate electrode connected to the first current controller; and 
 a second N-type transistor connected between the power line and the first P-type transistor to form the second current path, the second N-type transistor including a gate electrode connected to the second current controller. 
 
     
     
       3. The output buffer of  claim 2 , wherein the first current controller functions as a constant voltage source and a variable voltage source connected between the second input terminal and the gate electrode of the second P-type transistor, and
 the second current controller functions as a constant voltage source and a variable voltage source connected between the second input terminal and the gate electrode of the second N-type transistor. 
 
     
     
       4. The output buffer of  claim 2 , wherein the first current controller controls a voltage difference between a gate voltage of the first N-type transistor and a gate voltage of the second P-type transistor to be greater than a preset threshold. 
     
     
       5. The output buffer of  claim 2 , wherein the second current controller controls a voltage difference between a gate voltage of the second N-type transistor and a gate voltage of the first P-type transistor to be greater than a preset threshold. 
     
     
       6. The output buffer of  claim 2 , wherein the first current controller comprises:
 a fifth N-type transistor connected between the power line and the ground, the fifth N-type transistor including a gate electrode connected to a second node connected to the second input terminal; 
 a sixth N-type transistor connected between the second P-type transistor and the ground, the sixth N-type transistor including a gate electrode and a drain electrode connected to each other; 
 a seventh N-type transistor connected between a third node and the ground, the seventh N-type transistor including a gate electrode connected to the gate electrode of the sixth N-type transistor; and 
 a first resistor connected between the fifth N-type transistor and the third node, and 
 wherein the gate electrode of the second P-type transistor is connected to the third node. 
 
     
     
       7. The output buffer of  claim 6 , wherein the first current controller further comprises:
 an eighth P-type transistor connected between the power line and the fifth N-type transistor, the eighth N-type transistor including a gate electrode and a drain electrode connected to each other. 
 
     
     
       8. The output buffer of  claim 6 , wherein the sixth N-type transistor and the seventh N-type transistor are a current minor generating a current ratio of b:1 (where b is a real number of 1 or more), and
 wherein the third current flows through the seventh N-type transistor based on the first current. 
 
     
     
       9. The output buffer of  claim 6 , wherein the second current controller comprises:
 a fifth P-type transistor connected between the power line and the ground, the fifth P-type transistor including a gate electrode connected to a second node connected to the second input terminal; 
 a sixth P-type transistor connected between the power line and the second N-type transistor, the sixth P-type transistor including a gate electrode and a drain electrode connected to each other; 
 a seventh P-type transistor connected between a fourth node and the ground, the seventh P-type transistor including a gate electrode connected to the gate electrode of the sixth P-type transistor; and 
 a second resistor connected between the fourth node and the fifth P-type transistor, and 
 wherein the gate electrode of the second N-type transistor is connected to the fourth node. 
 
     
     
       10. The output buffer of  claim 9 , wherein the second current controller further comprises:
 an eighth N-type transistor that is connected between the fifth P-type transistor and the ground, the eighth N-type transistor including a gate electrode and a drain electrode connected to each other. 
 
     
     
       11. The output buffer of  claim 9 , wherein the sixth P-type transistor and the seventh P-type transistor are a current minor generating a current ratio of b:1 (where b is a real number of 1 or more), and
 wherein the fourth current flows through the seventh P-type transistor based on the second current. 
 
     
     
       12. The output buffer of  claim 9 , wherein the current supply circuit comprises:
 a first bias current source connected between the third node and the ground; and 
 a second bias current source connected between the power line and the fourth node. 
 
     
     
       13. The output buffer of  claim 2 , wherein the first current output comprises:
 a third P-type transistor connected between the power line and the first N-type transistor, the third P-type transistor including a gate electrode and a drain electrode connected to each other; and 
 a fourth P-type transistor connected between the power line and the output terminal, the fourth P-type transistor including a gate electrode connected to the gate electrode of the third P-type transistor. 
 
     
     
       14. The output buffer of  claim 2 , wherein the second current output comprises:
 a third N-type transistor connected between the first P-type transistor and the ground, the third N-type transistor including a gate electrode and a drain electrode connected to each other; and 
 a fourth N-type transistor connected between the output terminal and the ground, the fourth N-type transistor including a gate electrode connected to the gate electrode of the third N-type transistor. 
 
     
     
       15. A data driver comprising:
 a digital-to-analog converter configured to convert digital image data into an analog data signal; and 
 an output buffer configured to provide the analog data signal to a data line connected to the display panel, 
 wherein the output buffer comprises: 
 a buffer circuit configured to output the analog data signal to an output terminal based on a first input signal provided to a first input terminal and a second input signal provided to a second input terminal; and 
 a current supply circuit connected in parallel to the buffer circuit, and configured to provide an auxiliary current to the output terminal based on the first input signal and the second input signal, 
 wherein the analog data signal is provided to the second input terminal, 
 wherein the current supply circuit comprises: 
 a current source generator connected to the first input terminal and configured to generate a first current provided to a first current path or a second current provided to a second current path based on the first input signal and the analog data signal; 
 a first current controller connected between the second input terminal and the current source generator and configured to control the first current based on a third current generated by the first current; 
 a second current controller connected between the second input terminal and the current source generator and configured to control the second current based on a fourth current generate by the second current; 
 a first current output configured to provide a value obtained by multiplying the first current by k times (where k is a positive real number) as the auxiliary current to the output terminal; and 
 a second current output configured to allow a value obtained by multiplying the second current by K times (where K is a positive real number) as the auxiliary current to flow from the output terminal to a ground. 
 
     
     
       16. A display device comprising:
 a display panel including pixels; 
 a scan driver supplying scan signals to the pixels through scan lines; and 
 a data driver including a digital-to-analog converter for converting digital image data to an analog data signal, and an output buffer for providing the analog data signal to data lines connected to the display panel, 
 wherein the output buffer comprises: 
 a buffer circuit configured to output the analog data signal to an output terminal based on a first input signal provided to a first input terminal and a second input signal provided to a second input terminal; and 
 a current supply circuit connected in parallel to the buffer circuit, and configured to provide an auxiliary current to the output terminal based on the first input signal and the second input signal, 
 wherein the current supply circuit comprises: 
 a current source generator connected to the first input terminal and configured to generate a first current provided to a first current path or a second current provided to a second current path based on the first input signal and the second input signal; 
 a first current controller connected between the second input terminal and the current source generator and configured to control the first current based on a third current generated by the first current; 
 a second current controller connected between the second input terminal and the current source generator and configured to control the second current based on a fourth current generated by the second current; 
 a first current output configured to provide a value obtained by multiplying the first current by k times (where k is a positive real number) as the auxiliary current to the output terminal; and 
 a second current output configured to allow a value obtained by multiplying the second current by k times as the auxiliary current to flow from the output terminal to a ground, and 
 wherein the analog data signal is provided to the second input terminal.