Gate driving circuit, method of driving gate driving circuit, and display panel

Abstract

The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

What is claimed is: 
     
       1. A gate driving circuit comprising a plurality of driving units connected in cascade, wherein each driving unit of the plurality of driving units comprises:
 N shift register units; and 
 a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal; 
 wherein the plurality of resolution modes comprise a first resolution mode, a second resolution mode and a third resolution mode, and the mode control circuit is configured to: 
 in the first resolution mode, connect the N shift register units in cascade; 
 in the second resolution mode, divide the N shift register units into M groups, connect the M groups in cascade, and connect shift register units in each group of the M groups in parallel; and 
 in the third resolution mode, connect the N shift register units in parallel. 
 
     
     
       2. The gate driving circuit of  claim 1 , wherein N=4, M=2, the N shift register units comprise a first shift register unit, a second shift register unit, a third shift register unit and a fourth shift register unit, each shift register unit has a cascade input terminal and a first cascade output terminal, and the mode control circuit is configured to:
 in the first resolution mode, connect the first cascade output terminal of an nth shift register unit to the cascade input terminal of an (n+1)th shift register unit, and disconnect the cascade input terminal of the nth shift register unit from the cascade input terminal of the (n+1)th shift register unit, where 1≤n≤N−1; 
 in the second resolution mode, disconnect the first cascade output terminal of the first shift register unit from the cascade input terminal of the second shift register unit, connect the first cascade output terminal of the second shift register unit to the cascade input terminal of the third shift register unit, disconnect the first cascade output terminal of the third shift register unit from the cascade input terminal of the fourth shift register unit, connect the cascade input terminal of the first shift register unit to the cascade input terminal of the second shift register unit, and connect the cascade input terminal of the third shift register unit to the cascade input terminal of the fourth shift register unit; and 
 in the third resolution mode, disconnect the first cascade output terminal of the nth shift register unit from the cascade input terminal of the (n+1)th shift register unit, and connect the cascade input terminal of the nth shift register unit to the cascade input terminal of the (n+1)th shift register unit. 
 
     
     
       3. The gate driving circuit of  claim 2 , wherein each of the first shift register unit, the second shift register unit, the third shift register unit and the fourth shift register unit further has a reset terminal and a second cascade output terminal, and the mode control circuit is further configured to:
 in the first resolution mode, connect the reset terminal of the nth shift register unit to the second cascade output terminal of the (n+1)th shift register unit, and disconnect the reset terminal of the nth shift register unit from the reset terminal of the (n+1)th shift register unit; 
 in the second resolution mode, disconnect the reset terminal of the first shift register unit from the second cascade output terminal of the second shift register unit, connect the reset terminal of the second shift register unit to the second cascade output terminal of the third shift register unit, disconnect the reset terminal of the third shift register unit from the second cascade output terminal of the fourth shift register unit, connect the reset terminal of the first shift register unit to the reset terminal of the second shift register unit, disconnect the reset terminal of the second shift register unit from the reset terminal of the third shift register unit, and connect the reset terminal of the third shift register unit to the reset terminal of the fourth shift register unit; and 
 in the third resolution mode, disconnect the reset terminal of the nth shift register unit from the second cascade output terminal of the (n+1)th shift register unit, and connect the reset terminal of the nth shift register unit to the reset terminal of the (n+1)th shift register unit. 
 
     
     
       4. The gate driving circuit of  claim 2 , wherein the control signal comprises a first control signal, a second control signal, a third control signal and a fourth control signal, and the mode control circuit comprises:
 a first transistor having a gate electrode connected to receive the first control signal, a first electrode connected to the first cascade output terminal of the first shift register unit, and a second electrode connected to the cascade input terminal of the second shift register unit; 
 a second transistor having a gate electrode connected to receive the second control signal, a first electrode connected to the cascade input terminal of the first shift register unit, and a second electrode connected to the cascade input terminal of the second shift register unit; 
 a third transistor having a gate electrode connected to receive the third control signal, a first electrode connected to the first cascade output terminal of the second shift register unit, and a second electrode connected to the cascade input terminal of the third shift register unit; 
 a fourth transistor having a gate electrode connected to receive the fourth control signal, a first electrode connected to the cascade input terminal of the first shift register unit, and a second electrode connected to the cascade input terminal of the third shift register unit; 
 a fifth transistor having a gate electrode connected to receive the first control signal, a first electrode connected to the first cascade output terminal of the third shift register unit, and a second electrode connected to the cascade input terminal of the fourth shift register unit; and 
 a sixth transistor having a gate electrode connected to receive the second control signal, a first electrode connected to the cascade input terminal of the third shift register unit, and a second electrode connected to the cascade input terminal of the fourth shift register unit. 
 
     
     
       5. The gate driving circuit of  claim 4 , wherein the control signal further comprises a fifth control signal, and the mode control circuit further comprises:
 a seventh transistor having a gate electrode connected to receive the first control signal, a first electrode connected to the reset terminal of the first shift register unit, and a second electrode connected to the second cascade output terminal of the second shift register unit; 
 an eighth transistor having a gate electrode connected to receive the fifth control signal, a first electrode connected to the reset terminal of the first shift register unit, and a second electrode connected to the reset terminal of the second shift register unit; 
 a ninth transistor having a gate electrode connected to receive the third control signal, a first electrode connected to the reset terminal of the second shift register unit, and a second electrode connected to the second cascade output terminal of the third shift register unit; 
 a tenth transistor having a gate electrode connected to receive the fourth control signal, a first electrode connected to the reset terminal of the second shift register unit, and a second electrode connected to the reset terminal of the third shift register unit; 
 an eleventh transistor having a gate electrode connected to receive the first control signal, a first electrode connected to the reset terminal of the third shift register unit, and a second electrode connected to the second cascade output terminal of the fourth shift register unit; and 
 a twelfth transistor having a gate electrode connected to receive the second control signal, a first electrode connected to the reset terminal of the third shift register unit, and a second electrode connected to the reset terminal of the fourth shift register unit. 
 
     
     
       6. The gate driving circuit of  claim 2 , wherein the first cascade output terminal of an Nth shift register unit in an ith stage driving unit is connected to the cascade input terminal of the first shift register unit in an (i+1)th stage driving unit; wherein the reset terminal of the Nth shift register unit in the ith stage driving unit is connected to the second cascade output terminal of the first shift register unit in the (i+1)th stage driving unit. 
     
     
       7. The gate driving circuit of  claim 1 , wherein the plurality of driving units are divided into a plurality of groups, and each group of driving units are connected to a group of control signal lines so as to receive the control signal for the group of driving units. 
     
     
       8. The gate driving circuit of  claim 2 , wherein each shift register unit comprises:
 a first shift register having an input terminal serving as the cascade input terminal of the shift register unit, and an output terminal serving as the second cascade output terminal of the shift register unit; 
 a second shift register having an input terminal connected to the output terminal of the first shift register; and 
 a third shift register having an input terminal connected to an output terminal of the second shift register, and an output terminal serving as the first cascade output terminal of the shift register unit. 
 
     
     
       9. A method of driving the gate driving circuit  claim 1 , comprising:
 receiving, by a mode control circuit of each driving unit in a plurality of driving units, a control signal for the driving unit, and connecting the N shift register units in one of a plurality of resolution modes under the control of the control signal; and 
 generating output signals by the N shift register units connected in each driving unit. 
 
     
     
       10. The method of  claim 9 , wherein the plurality of resolution modes comprise a first resolution mode, a second resolution mode and a third resolution mode, and wherein,
 in the first resolution mode, the mode control circuit is configured to connect the N shift register units in cascade, so that the N shift register units generate sequentially shifted output signals; 
 in the second resolution mode, the mode control circuit is configured to divide the N shift register units into M groups, connect the M groups in cascade, and connect shift register units in each group of the M groups in parallel, so that the shift register units in each group generate output signals in parallel, and a group of output signals generated by an (m+1)th group of shift register units are shifted with respect to a group of output signals generated by an mth group of shift register units, where m is an integer, and 1≤m≤M−1; and 
 in the third resolution mode, the mode control circuit is configured to connect the N shift register units in parallel, so that the N shift register units generate output signals in parallel. 
 
     
     
       11. The method of  claim 10 , wherein N=4, M=2, and the N shift register units comprise a first shift register unit, a second shift register unit, a third shift register unit and a fourth shift register unit, and wherein,
 in the first resolution mode, the mode control circuit is configured to connect a first cascade output terminal of an nth shift register unit to a cascade input terminal of an (n+1)th shift register unit, and disconnect a cascade input terminal of the nth shift register unit from the cascade input terminal of the (n+1)th shift register unit, where 1≤n≤N−1; 
 in the second resolution mode, the mode control circuit is configured to disconnect a first cascade output terminal of the first shift register unit from a cascade input terminal of the second shift register unit, connect the cascade input terminal of the second shift register unit to a cascade input terminal of the first shift register unit, connect a first cascade output terminal of the second shift register unit to a cascade input terminal of the third shift register unit, disconnect the cascade input terminal of the third shift register unit from the cascade input terminal of the second shift register unit, disconnect a first cascade output terminal of the third shift register unit from a cascade input terminal of the fourth shift register unit, and connect the cascade input terminal of the third shift register unit to the cascade input terminal of the fourth shift register unit; and 
 in the third resolution mode, the mode control circuit is configured to disconnect the first cascade output terminal of the nth shift register unit from the cascade input terminal of the (n+1)th shift register unit, and connect the cascade input terminal of the nth shift register unit to the cascade input terminal of the (n+1)th shift register unit. 
 
     
     
       12. The method of  claim 11 , further comprising:
 in the first resolution mode, connecting, by the mode control circuit, a reset terminal of the nth shift register unit to a second cascade output terminal of the (n+1)th shift register unit, and disconnecting the reset terminal of the nth shift register unit from a reset terminal of the (n+1)th shift register unit; 
 in the second resolution mode, disconnecting, by the mode control circuit, the reset terminal of the first shift register unit from the second cascade output terminal of the second shift register unit, connecting the reset terminal of the second shift register unit to the second cascade output terminal of the third shift register unit, disconnecting the reset terminal of the third shift register unit from the second cascade output terminal of the fourth shift register unit, connecting the reset terminal of the first shift register unit to the reset terminal of the second shift register unit, and connecting the reset terminal of the third shift register unit to the reset terminal of the fourth shift register unit; and 
 in the third resolution mode, disconnecting, by the mode control circuit, the reset terminal of the nth shift register unit from the second cascade output terminal of the (n+1)th shift register unit, and connecting the reset terminal of the nth shift register unit to the reset terminal of the (n+1)th shift register unit. 
 
     
     
       13. The method of  claim 11 , wherein the mode control circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and wherein,
 in the first resolution mode, a first control signal and a third control signal are at a first level, and a second control signal and a fourth control signal are at a second level, so that the first transistor, the third transistor and the fifth transistor are turned on, and the second transistor, the fourth transistor and the sixth transistor are turned off; 
 in the second resolution mode, the second control signal and the third control signal are at the first level, and the first control signal and the fourth control signal are at the second level, so that the second transistor, the third transistor and the sixth transistor are turned on, and the first transistor, the fourth transistor and the fifth transistor are turned off; and 
 in the third resolution mode, the second control signal and the fourth control signal are at the first level, and the first control signal and the third control signal are at the second level, so that the second transistor, the fourth transistor and the sixth transistor are turned on, and the first transistor, the third transistor and the fifth transistor are turned off. 
 
     
     
       14. The method of  claim 13 , wherein the mode control circuit further comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, and wherein,
 in the first resolution mode, a fifth control signal is at the second level, so that the seventh transistor, the ninth transistor and the eleventh transistor are turned on, and the eighth transistor, the tenth transistor and the twelfth transistor are turned off; 
 in the second resolution mode, the fifth control signal is at the first level, so that the eighth transistor, the ninth transistor and the twelfth transistor are turned on, and the seventh transistor, the tenth transistor and the eleventh transistor are turned off; and 
 in the third resolution mode, the fifth control signal is at the second level, so that the tenth transistor and the twelfth transistor are turned on, and the seventh transistor, the eighth transistor, the ninth transistor and the eleventh transistor are turned off.