US11837654B2ActiveUtilityA1

Method for controlling semiconductor device

72
Assignee: TOSHIBA KKPriority: Nov 1, 2019Filed: Dec 20, 2022Granted: Dec 5, 2023
Est. expiryNov 1, 2039(~13.3 yrs left)· nominal 20-yr term from priority
H02M 3/003H10D 12/481H10D 64/513H10D 62/126H10D 62/105H10D 64/117H01L 29/7397H02M 1/08H02M 7/003H02M 7/5387H03K 17/168H02M 1/0054Y02B70/10H03K 2217/0045
72
PatentIndex Score
0
Cited by
22
References
20
Claims

Abstract

A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for controlling a semiconductor device, the semiconductor device including:
 a semiconductor part provided between a first electrode and a second electrode; 
 at least a control electrode being provided between the semiconductor part and the first electrode; 
 a first insulating film provided between the semiconductor part and the control electrode; and 
 a second insulating film provided between the first electrode and the control electrode; 
 the semiconductor part including first to fifth semiconductor layers, the first, third and fifth semiconductor layers being of a first conductivity type, the second and fourth semiconductor layers being of a second conductivity type, 
 the second semiconductor layer being provided between the first semiconductor layer and the first electrode, the second semiconductor layer including a portion facing the control electrode via the first insulating film, 
 the third semiconductor layer being provided between the second semiconductor layer and the first electrode, the third semiconductor layer contacting the first insulating film, 
 the fourth semiconductor layer being provided between the first semiconductor layer and the second electrode, 
 the fifth semiconductor layer being provided between the first semiconductor layer and the second electrode, the fourth and fifth semiconductor layers being arranged along the second electrode, 
 the first electrode being electrically connected to the second and third semiconductor layers, 
 the second electrode being electrically connected to the fourth and fifth semiconductor layers, 
 
       the method comprising:
 applying a first control voltage between the first electrode and the control electrode in a first period; 
 applying a second control voltage between the first electrode and the control electrode in a second period after the first period, the second control voltage being greater than the first control voltage; and 
 applying a third control voltage between the first electrode and the control electrode in a third period after the second period, the third control voltage being greater than the first control voltage and less than the second control voltage. 
 
     
     
       2. The method according to  claim 1 , wherein
 the first control voltage is a negative voltage with respect to a potential of the first electrode, and 
 the second control voltage is a positive voltage with respect to the potential of the first electrode. 
 
     
     
       3. The method according to  claim 2 , wherein
 an absolute value of the first control voltage is equal to an absolute value of the second control voltage. 
 
     
     
       4. The method according to  claim 1 , wherein
 the second control voltage is applied so that a potential difference between the control electrode and the first electrode is greater than a threshold voltage of the control electrode. 
 
     
     
       5. The method according to  claim 1 , wherein
 the third control voltage is less than a threshold voltage of the control electrode. 
 
     
     
       6. The method according to  claim 5 , wherein
 the third control voltage is a positive voltage. 
 
     
     
       7. The method according to  claim 1 , wherein
 a p-n junction is provided between the first semiconductor layer and the second semiconductor layer, the p-n junction being biased in a forward direction before the first period and during the first to third periods and being biased in a reverse direction after the third period. 
 
     
     
       8. The method according to  claim 7 , wherein
 the third control voltage is continually applied between the first electrode and the control electrode after the p-n junction is biased in the reverse direction at an end of the third period. 
 
     
     
       9. The method according to  claim 8 , wherein
 the third control voltage is continually applied between the first electrode and the control electrode in a fourth period after the third period, and 
 the first control voltage is applied between the first electrode and the control electrode at an end of the fourth period. 
 
     
     
       10. The method according to  claim 1 , wherein
 the semiconductor device includes a plurality of the control electrodes, the control electrodes including first and second control electrodes; 
 the first to third control voltages are applied to the first control electrode in the first to third periods, respectively, and 
 the first and second control voltages are applied between the first electrode and the second control electrode in the first and second periods, respectively, and 
 a fourth control voltage is applied between the second control electrode and the first electrode in the third period, the fourth control voltage being less than the third control voltage. 
 
     
     
       11. The method according to  claim 10 , wherein
 the fourth control voltage is equal to the first control voltage. 
 
     
     
       12. The method according to  claim 10 , wherein
 a p-n junction is provided between the first semiconductor layer and the second semiconductor layer, the p-n junction being biased in a forward direction before the first period and during the first to third periods and being biased in a reverse direction after the third period; and 
 the fourth control voltage is continually applied between the first electrode and the second control electrode after the p-n junction is biased in the reverse direction at an end of the third period. 
 
     
     
       13. The method according to  claim 10 , wherein
 the first control voltage applied between the first electrode and the first control electrode is different from the first control voltage applied between the first electrode and the second control electrode, and 
 the second control voltage applied between the first electrode and the first control electrode is different from the second control voltage applied between the first electrode and the second control electrode. 
 
     
     
       14. The method according to  claim 13 , wherein
 the control electrodes include two or more of the third control electrodes, and 
 the two or more of the third control electrodes are provided between the first control electrode and the second control electrode. 
 
     
     
       15. The method according to  claim 1 , wherein
 the semiconductor device includes a plurality of the control electrodes, the control electrodes including first to third control electrodes; 
 the third control electrode is provided between the first control electrode and the second control electrode; 
 the first to third control voltages are applied between the first electrode and the first control electrode and between the first electrode and the second control electrode, the first to third control voltages being applied in the first to third periods, respectively, and 
 the third control electrode is maintained at a potential same as a potential of the first electrode in the first to third periods. 
 
     
     
       16. A method for controlling a power conversion device,
 the power conversion device including a plurality of semiconductor devices, each of the plurality of semiconductor devices including:
 a semiconductor part provided between a first electrode and a second electrode; 
 at least a control electrode provided between the semiconductor part and the first electrode, 
 a first insulating film provided between the semiconductor part and the control electrode; and 
 a second insulating film provided between the first electrode and the control electrode; 
 the semiconductor part including first to fifth semiconductor layers, the first, third and fifth semiconductor layers being of a first conductivity type, the second and fourth semiconductor layers being of a second conductivity type, 
 the second semiconductor layer being provided between the first semiconductor layer and the first electrode and including a portion facing the control electrode via the first insulating film, 
 the third semiconductor layer being provided between the second semiconductor layer and the first electrode, the third semiconductor layer contacting the first insulating film, 
 the fourth semiconductor layer being provided between the first semiconductor layer and the second electrode, 
 the fifth semiconductor layer being provided between the first semiconductor layer and the second electrode, the fourth and fifth semiconductor layers being arranged along the second electrode, 
 the first electrode being electrically connected to the second and third semiconductor layers, 
 the second electrode being electrically connected to the fourth and fifth semiconductor layers, 
 
 the plurality of semiconductor devices including first and second semiconductor devices connected in series, 
 the method comprising:
 biasing the first semiconductor device in a forward direction at a first timing by turning off the second semiconductor device while, in the first semiconductor device, a first control voltage is applied between the first electrode and the control electrode, the first control voltage being less than a threshold voltage of the control electrode, the second semiconductor device being turned off by reducing a control voltage of the second semiconductor device applied between the first electrode and the control electrode, the control voltage of the second semiconductor device being reduced from a second control voltage to the first control voltage, the second control voltage being greater than the threshold voltage of the control electrode; 
 increasing a control voltage of the first semiconductor device applied between the first electrode and the control electrode, the control voltage of the first semiconductor device being increased from the first control voltage to the second control voltage at a second timing after the first timing; 
 reducing the control voltage of the first semiconductor device from the second control voltage to a third control voltage at a third timing after the second timing, the third control voltage being greater than the first control voltage and less than the second control voltage; and 
 turning on the second semiconductor device at a fourth timing after the third timing by increasing the control voltage of the second semiconductor device from the first control voltage to the second control voltage. 
 
 
     
     
       17. The method according to  claim 16 , wherein
 the first control voltage is a negative voltage with respect to a potential of the first electrode, and 
 the second control voltage is a positive voltage with respect to the potential of the first electrode. 
 
     
     
       18. The method according to  claim 16 , wherein
 the third control voltage is a positive voltage less than the threshold voltage of the control electrode. 
 
     
     
       19. The method according to  claim 16 , wherein
 the control voltage of the first semiconductor device is reduced from the third control voltage to a fourth control voltage at a fifth timing after the fourth timing, the fourth control voltage being less than the third control voltage. 
 
     
     
       20. The method according to  claim 19 , wherein
 the fourth control voltage is equal to the first control voltage.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.