Temperature-sensitive transistor gate driver

Abstract

A system comprises a gate driver that is configured to couple to a transistor disposed in a transistor module via a first pin. The gate driver comprises a duty cycle measurement circuit having a first input terminal and a first output terminal, the first input terminal coupled to a second pin via an isolator. The duty cycle measurement circuit comprises a flip-flop, a counter, a shift register, and a comparator. The system comprises an analog to digital converter circuit having a second input terminal, a second output terminal, and a reference terminal, the second input terminal coupled to a third pin configured to couple to a temperature-sensitive device disposed in the transistor module, the second output terminal coupled to a fourth pin via the isolator, and the reference terminal coupled to the first output terminal.

What is claimed is: 
     
       1. A gate driver, comprising:
 a duty cycle measurement circuit having a duty cycle input and a duty cycle output, wherein the duty cycle measurement circuit is configured to provide a start of conversion (SOC) signal at the duty cycle output, and the duty cycle measurement circuit includes:
 a flip-flop having a flip-flop input and a flip-flop output, wherein the flip-flop input is coupled to the duty cycle input; 
 a counter having a counter input and a counter output, wherein the counter input is coupled to the flip-flop output; 
 a shift register having a shift input and a shift output, wherein the shift input is coupled to the counter output; and 
 a comparator having first and second comparator inputs and a comparator output, wherein the first comparator input is coupled to the shift output; and 
 
 an analog to digital converter (ADC) having an ADC input, an ADC output, and a reference terminal, wherein the reference terminal is coupled to the duty cycle output. 
 
     
     
       2. The gate driver of  claim 1 , further comprising a current source coupled to the ADC input. 
     
     
       3. The gate driver of  claim 1 , wherein the duty cycle measurement circuit is configured to:
 receive a pulse width modulated (PWM) signal; and 
 produce the SOC signal responsive to a turn-on time of the PWM signal. 
 
     
     
       4. The gate driver of  claim 1 , wherein the gate driver is adapted to be coupled to a control terminal of a transistor in a transistor module, and the ADC input is adapted to be coupled to a temperature sensitive device in the transistor module. 
     
     
       5. The gate driver of  claim 4 , wherein the ADC is configured to:
 sample a voltage across the temperature sensitive device in response to receiving the SOC signal; and 
 produce a data frame responsive to the sampled voltage across the temperature sensitive device. 
 
     
     
       6. The gate driver of  claim 5 , wherein the data frame includes an indication of the sampled voltage across the temperature sensitive device. 
     
     
       7. The gate driver of  claim 5 , wherein the temperature sensitive device is a diode. 
     
     
       8. The gate driver of  claim 1 , further comprising an isolator coupled between the duty cycle input and the ADC output. 
     
     
       9. The gate driver of  claim 8 , further comprising:
 a communication interface having first and second communication ports, wherein the first communication port is coupled to the isolator; and 
 an adding unit having an adding unit input and an adding unit output, wherein the adding unit output is coupled to the second communication port through the isolator, and the adding unit input is coupled to the ADC output. 
 
     
     
       10. The gate driver of  claim 9 , further comprising a controller unit coupled to the second communication port. 
     
     
       11. A method of gate driving, the method comprising:
 receiving, by a duty cycle measurement circuit, a pulse width modulation (PWM) signal; 
 producing, by the duty cycle measurement circuit, a start of conversion (SOC) signal based on a turn-on time of the PWM signal; 
 receiving, by an analog to digital converter (ADC), an analog signal indicating a voltage across a temperature sensitive device; and 
 producing, by the ADC in response to receiving the SOC signal, a digital signal representative of the analog signal. 
 
     
     
       12. The method of  claim 11 , wherein the temperature sensitive device is in proximity to and indicating a temperature of a transistor. 
     
     
       13. The method of  claim 12 , further comprising providing, by a current source, a current signal to the temperature sensitive device. 
     
     
       14. The method of  claim 11 , further comprising:
 receiving, by an adding unit, information pertaining to the PWM signal and the digital signal; and 
 concatenating, by the adding unit, the information pertaining to the PWM signal and the digital signal to produce a combined signal. 
 
     
     
       15. The method of  claim 14 , further comprising communicating the combined signal over a communication interface between the adding unit and a controller. 
     
     
       16. A system for transistor gate drive, comprising:
 a gate driver comprising:
 a duty cycle measurement circuit having a duty cycle input and a duty cycle output, wherein the duty cycle measurement circuit is configured to provide a start of conversion (SOC) signal at the duty cycle output, and the duty cycle measurement circuit includes:
 a flip-flop having a flip-flop input and a flip-flop output, wherein the flip-flop input is coupled to the duty cycle input; 
 a counter having a counter input and a counter output, wherein the counter input is coupled to the flip-flop output; 
 a shift register having a shift input and a shift output, wherein the shift input is coupled to the counter output; and 
 a comparator having first and second comparator inputs and a comparator output, wherein the first comparator input is coupled to the shift output; 
 
 an analog to digital converter (ADC) having an ADC input, an ADC output, and a reference terminal, wherein the reference terminal is coupled to the duty cycle output, and the ADC input is coupled to a temperature sensitive device; and 
 
 an adding unit having first and second adding unit inputs and an adding unit output, wherein the first adding unit input is coupled to the ADC output, and the second adding unit input is coupled to the duty cycle output; 
 a communication interface coupled to the adding unit output through a galvanic isolator; and 
 a controller unit coupled to the communication interface. 
 
     
     
       17. The system of  claim 16 , wherein the controller unit is coupled to the duty cycle input. 
     
     
       18. The system of  claim 16 , wherein the gate driver further comprises a current source coupled to the ADC input. 
     
     
       19. The system of  claim 16 , wherein the duty cycle measurement circuit is configured to:
 receive a pulse width modulated (PWM) signal; and 
 produce a start of conversion (SOC) signal responsive to a turn-on time of the PWM signal. 
 
     
     
       20. The system of  claim 16 , wherein the gate driver is coupled to a transistor in a transistor module, and the temperature sensitive device is included in the transistor module.