Memory system for performing cache program operation and operating method thereof

Abstract

A memory device includes a memory block including a plurality of pages, a peripheral circuit configured to perform a first program operation for storing first page data and a second program operation for storing second page data after the first program operation, a status register configured to store status information, a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller when the first program operation is being performed, and a status register controller configured to store in the status register first failure information indicating whether the first program operation passes, store in the status register validity information indicating whether the first failure information is valid information within a predetermined time period from when the second program operation starts, and provide the external controller with the status information including the first failure information and the validity information.

What is claimed is: 
     
       1. A memory device, comprising:
 a memory block including a plurality of pages; 
 a peripheral circuit configured to perform a first program operation for storing first page data in a first page among the plurality of pages and perform a second program operation for storing second page data in a second page among the plurality of pages after the first program operation; 
 a status register configured to store status information including information related to each of the first program operation and the second program operation; 
 a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller while the first program operation is performed; and 
 a status register controller configured to: 
 store, in the status register, first failure information indicating whether the first program operation passes or fails after the second program operation starts; 
 store, in the status register, a first value of validity information indicating that the first failure information is valid within a predetermined time period from when the second program operation starts; and 
 provide the external controller with the status information including the first failure information and the first value of the validity information which is stored in the status register, 
 wherein the status register controller is configured to provide the external controller with a second value of the validity information indicating that the first failure information is invalid, during a time period between when the second page data is loaded and when the first failure information is stored in the status register. 
 
     
     
       2. The memory device of  claim 1 , wherein the predetermined time period is a time period from when the second program operation starts to when a state of the peripheral circuit is changed from a busy state incapable of loading data to a ready state capable of loading the data. 
     
     
       3. The memory device of  claim 1 , wherein the status register controller is configured to:
 store the first failure information in a first bit of the status register after the first program operation ends; 
 store the first failure information stored in the first bit of the status register in a second bit of the status register; and 
 store the validity information in a third bit of the status register within the predetermined time period from when the second program operation starts. 
 
     
     
       4. The memory device of  claim 3 , wherein the status information includes the first failure information stored in the second bit of the status register and the validity information stored in the third bit of the status register. 
     
     
       5. The memory device of  claim 3 , wherein the status register controller comprises:
 a mask signal generating circuit configured to generate a mask signal indicating that the first failure information is invalid during the time period between when the second page data is loaded and when the first failure information is stored in the second bit of the status register; and 
 a validity information generating circuit configured to generate the validity information based on a cache program signal indicating progress status of the first program operation or the second program operation and the mask signal. 
 
     
     
       6. The memory device of  claim 3 ,
 wherein the status register controller is further configured to store second failure information indicating whether the second program operation passes or fails in the first bit of the status register after the second program operation starts, and 
 wherein the status information includes the second failure information stored in the first bit of the status register. 
 
     
     
       7. The memory device of  claim 1 , wherein the status register controller is configured to:
 store, when the first program operation is completed within a predetermined time limit, the first failure information indicating that the first program operation for storing the first page data in the first page passes in the status register; and 
 store, when the first program operation is not completed within the predetermined time limit, the first failure information indicating that the first program operation for storing the first page data in the first page fails in the status register. 
 
     
     
       8. A memory controller configured to control a memory device including a plurality of pages, the memory controller comprising:
 a data buffer configured to store page data to be stored in the memory device; and 
 a processor configured to: 
 provide the memory device with first page data to be stored in a first page among the plurality of pages; 
 provide the memory device with second page data to be stored in a second page while the memory device performs a first program operation for storing the first page data; and 
 obtain status information indicating an internal state of the memory device from the memory device before the memory device ends a second program operation for storing the second page data, 
 wherein the status information includes failure information indicating whether the first program operation passes or fails and validity information indicating whether the failure information is valid or invalid, and 
 wherein the processor is further configured to: 
 obtain a first value of the validity information, indicating that the failure information is invalid, during a time period between when the second page data is provided to the memory device and when the memory device starts the second program operation; and 
 obtain a second value of the validity information, indicating that the failure information is valid, after the memory device starts the second program operation. 
 
     
     
       9. The memory controller of  claim 8 ,
 wherein the processor is further configured to provide the memory device with a status read command for requesting the status information, and 
 wherein the processor obtains the status information, which is provided in response to the status read command. 
 
     
     
       10. The memory controller of  claim 9 ,
 wherein the processor is further configured to: 
 provide the memory device with the status read command for requesting the status information, and 
 obtain the status information, which is provided within a predetermined time period in response to the status read command, and 
 wherein the predetermined time period is a time period from when the second program operation starts to when a state of the memory device is changed from a busy state incapable of loading data to a ready state capable of loading the data. 
 
     
     
       11. The memory controller of  claim 9 , wherein the processor is further configured to:
 when a value of the validity information is the first value, provide the memory device with the status read command again, and 
 obtain the status information, which indicates a current internal state of the memory device. 
 
     
     
       12. The memory controller of  claim 8 , wherein, when a value of the validity information is the second value and the failure information indicates that the first program operation fails, the processor is further configured to provide the memory device with the first page data and a program command to control the memory device to store the first page data in another page among the plurality of pages. 
     
     
       13. The memory controller of  claim 8 , wherein, when a value of the validity information is the second value and the failure information indicates that the first program operation passes, the processor is further configured to control the data buffer to remove the first page data from the data buffer. 
     
     
       14. A memory system, comprising:
 a memory device configured to: 
 while a first program operation for storing first data in a selected page among a plurality of pages is performed, load second data to be stored in a next page of the selected page; and 
 perform a second program operation for storing the second data in the next page after the first program operation ends; and 
 a memory controller configured to obtain status information including first failure information indicating whether the first program operation passes or fails and validity information indicating whether the first failure information is valid, the status information being provided from the memory device, 
 wherein the validity information, which is provided from the memory device within a predetermined time period from when the second program operation starts, comprises a first value indicating that the first failure information is valid, and 
 wherein the validity information, which is provided from the memory device during a time period between when the second data is loaded and when the second program operation starts, comprises a second value indicating that the first failure information is invalid. 
 
     
     
       15. The memory system of  claim 14 , wherein the predetermined time period is a time period from when the second program operation starts to when a state of the memory device is changed from a busy state incapable of loading data to a ready state capable of loading the data. 
     
     
       16. The memory system of  claim 14 ,
 wherein the memory device includes a status register configured to store the status information, 
 wherein the memory device is further configured to: 
 store the first failure information in a first bit of the status register after the first program operation ends, 
 store the first failure information stored in the first bit of the status register in a second bit of the status register, 
 store the validity information in a third bit of the status register, and 
 store second failure information indicating whether the second program operation passes or fails in the first bit of the status register when the second program operation starts, and 
 wherein the status information includes the second failure information stored in the first bit of the status register, the first failure information stored in the second bit of the status register, and the validity information stored in the third bit of the status register. 
 
     
     
       17. The memory system of  claim 16 , wherein the memory controller is further configured to determine whether the first failure information stored in the second bit is valid based on the validity information stored in the third bit. 
     
     
       18. The memory system of  claim 17 , wherein, when the validity information comprises the first value and the first failure information indicates that the first program operation fails, the memory controller is further configured to provide the memory device with the first data and a program command to control the memory device to store the first data in another page among the plurality of pages. 
     
     
       19. The memory system of  claim 17 ,
 further comprising a data buffer configured to temporarily store the first data or the second data to be stored in the memory device, 
 wherein, when the validity information comprises the first value and the first failure information indicates that the first program operation passes, the memory controller is further configured to control the data buffer to remove the first data therefrom. 
 
     
     
       20. The memory system of  claim 17 ,
 wherein the memory controller is further configured to provides the memory device with a status read command for requesting the status information, 
 wherein the memory controller obtains the status information, which is provided from the memory device in response to the status read command, and 
 wherein the memory controller is further configured to provide, when the validity information comprises the second value, the memory device with the status read command again.