Semiconductor device without a break region

Abstract

A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first inverter configured to receive a first signal, and generate a second signal by inverting the first signal; and 
 a second inverter configured to receive the second signal, and generate the first signal by inverting the second signal, 
 wherein the first inverter includes, 
 a first active fin extending in a first direction, 
 a second active fin spaced apart from the first active fin and extending in the first direction, 
 a third active fin extending in the first direction and being adjacent to the first active fin; and 
 a fourth active fin spaced apart from the third active fin and being adjacent to the second active fin and extending in the first direction, 
 a first gate line extending in a second direction, the second direction intersecting the first direction, the first gate line overlapping the first, second, third, and fourth active fins, 
 a second gate line extending in the second direction and spaced apart from the first gate line, the second gate line overlapping the first and second active fins, 
 a first metal line electrically connecting the first and second gate lines, the first metal line configured to provide the first signal to both the first gate line and the second gate line, 
 a second metal line electrically connected to a part of the first active fin between the first gate line and the second gate line and a part of the second active fin between the first gate line and the second gate line, the second metal line configured to transmit the second signal in response to the first signal, and 
 a third gate line disposed to overlap the first, the second, the third, and the fourth active fins, and spaced apart from the first gate line, the second gate line, and the first metal line. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein
 the first gate line includes a first P-type Metal-Oxide-Semiconductor (PMOS) transistor and a first N-type Metal-Oxide-Semiconductor (NMOS) transistor; 
 the first PMOS transistor includes a first source node that is connected to a driving power supply; and 
 the first NMOS transistor includes a second source node that is connected to ground. 
 
     
     
       3. The semiconductor device of  claim 2 , further comprising:
 a second PMOS transistor and a second NMOS transistor, the second PMOS transistor and the second NMOS transistor both including the second gate line, 
 wherein the second PMOS transistor is configured to share a first drain region with the first PMOS transistor, and 
 the first drain region is electrically connected to the second metal line. 
 
     
     
       4. The semiconductor device of  claim 3 , wherein:
 the second NMOS transistor is configured to share a second drain region with the first NMOS transistor; and 
 the second drain region is electrically connected to the second metal line. 
 
     
     
       5. The semiconductor device of  claim 1 , wherein the second inverter includes:
 a third gate line disposed to overlap the first and second active fins; 
 a fourth gate line spaced apart from the first, the second, and the third gate lines and disposed to overlap the first active fin; and 
 a fifth gate line spaced apart from the first, the second, the third, and the fourth gate lines, and disposed to overlap the second active fin. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein:
 the third gate line is configured to receive the second signal; 
 the fourth gate line is configured to receive a third signal; 
 the fifth gate line is configured to receive a fourth signal; and 
 the second, the third, and the fourth signals are different signals. 
 
     
     
       7. A semiconductor device, comprising:
 a first inverter configured to receive a first signal, and generate a second signal by inverting the first signal; and 
 a second inverter configured to receive the second signal, and generate the first signal by inverting the second signal, 
 wherein the first inverter includes, 
 a first multi-channel active pattern extending in a first direction, 
 a second multi-channel active pattern spaced apart from the first multi-channel active pattern and extending in the first direction, 
 a first gate line extending in a second direction, the second direction intersecting the first direction, the first gate line overlapping the first and second multi-channel active patterns, 
 a second gate line extending in the second direction and spaced apart from the first gate line, the second gate line overlapping the first and second multi-channel active patterns, 
 a first metal line electrically connecting the first and second gate lines, the first metal line configured to provide the first signal to both the first gate line and the second gate line, 
 a second metal line electrically connected to apart of the first multi-channel active pattern between the first gate line and the second gate line and a part of the second multi-channel active pattern between the first gate line and the second gate line, the second metal line configured to transmit the second signal in response to the first signal, and 
 a third gate line disposed to overlap the first and second multi-channel active patterns, and spaced apart from the first gate line, the second gate line, and the first metal line. 
 
     
     
       8. The semiconductor device of  claim 7 , wherein:
 the first multi-channel active pattern includes a first active pattern, and a second active pattern being adjacent to the first active pattern; and 
 the second multi-channel active pattern includes a third active pattern spaced apart from the first and second active patterns, and a fourth active pattern being adjacent to the third active pattern.