US11843008B2ActiveUtilityA1

SPAD pixel

71
Assignee: ST MICROELECTRONICS CROLLES 2 SASPriority: Oct 12, 2020Filed: Oct 11, 2021Granted: Dec 12, 2023
Est. expiryOct 12, 2040(~14.3 yrs left)· nominal 20-yr term from priority
H10F 39/809H10F 30/225H10F 39/18H10F 39/811H10F 39/018H10F 39/8033H01L 27/1461G01J 1/44H01L 27/14634H01L 31/107H04N 25/70G01J 2001/4466
71
PatentIndex Score
0
Cited by
4
References
5
Claims

Abstract

An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A method of manufacturing an electronic device which includes a stack of a first level comprising a SPAD, a second level comprising a quench circuit for said SPAD, and a third level comprising a circuit for processing data generated by said SPAD, the method comprising:
 a) forming said first level consisting of a first semiconductor layer including a SPAD and a first insulating layer; 
 b) forming a stack of layers of the second level comprising a second semiconductor layer, a first interconnection layer including first pads and a second insulating layer; 
 c) bonding by molecular bonding the second insulating layer of said stack of layers to the first insulating layer of the first level; 
 d) forming said quench circuit in the second semiconductor layer; 
 e) forming a stack of layers of the third level comprising a third semiconductor layer and a second interconnection layer including second pads; and 
 f) bonding by hybrid bonding the first and second interconnection layers and first and second pads. 
 
     
     
       2. The method according to  claim 1 , wherein the second semiconductor layer is etched, after step c), to form a plurality of distinct regions. 
     
     
       3. The method according to  claim 1 , wherein the first level comprises no electronic component other than the SPAD. 
     
     
       4. The method of  claim 1 , wherein the first level comprises a single SPAD. 
     
     
       5. The method of  claim 1 , wherein the second level only comprises said quench circuit.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.