Field effect transistor including multiple aspect trapping ratio structures

Abstract

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

What is claimed: 
     
       1. A method of fabricating a field-effect transistor, comprising:
 forming a device isolation layer, the device isolation layer including a lower trench that extends in a first direction and exposes a portion of a semiconductor substrate; 
 forming a mask pattern on the device isolation layer, the mask pattern having upper trenches crossing the lower trench and extending in a second direction that is different from the first direction; and 
 forming an epitaxial layer in the lower trench and the upper trenches, wherein the epitaxial layer comprises a semiconductor material having a lattice constant is different from that of the semiconductor substrate, and wherein the epitaxial layer includes a lower portion in the lower trench and upper portions in the upper trenches. 
 
     
     
       2. The method of  claim 1 , wherein a height of the lower trench is greater than two times a width of the lower trench, and
 a length of the lower trench is greater than the height of the lower trench. 
 
     
     
       3. The method of  claim 1 , wherein a height of the upper trenches is greater than two times a width of the upper trenches. 
     
     
       4. The method of  claim 1 , wherein forming the lower trench comprises:
 etching a second portion of the semiconductor substrate to form a device isolation trench defining preliminary active patterns; 
 forming the device isolation layer in the device isolation trench; and 
 etching the preliminary active patterns to expose a sidewall of the device isolation layer. 
 
     
     
       5. The method of  claim 1 , further comprising:
 forming a first insulating separation pattern to cross the upper portions of the epitaxial layer and to divide the epitaxial layer into a plurality of epitaxial patterns; and 
 forming a second insulating separation pattern to cross the lower portion of the epitaxial layer and to divide each epitaxial pattern of the plurality of epitaxial patterns into a plurality of fin structures. 
 
     
     
       6. A method of fabricating a field-effect transistor, comprising:
 forming a device isolation layer on a substrate, the device isolation layer including a lower trench that extends in a first direction; 
 forming a mask pattern on the device isolation layer, the mask pattern including upper trenches crossing the lower trench and extending in a second direction that is different from the first direction; 
 performing a selective epitaxial growth to form an epitaxial layer, the epitaxial layer including a lower portion in the lower trench and upper portions in the upper trenches; 
 forming a gate structure crossing the upper portions of the epitaxial layer; and 
 forming source and drain patterns on the upper portions at both sides of the gate structure, 
 wherein the substrate comprises a first semiconductor material having a first lattice constant, and 
 the epitaxial layer comprises a second semiconductor material having a second lattice constant that is different from the first lattice constant. 
 
     
     
       7. The method of  claim 6 , wherein the lower trench has a first length in the first direction and a first width in the second direction,
 the first length is greater than a depth of the lower trench, and 
 the depth of the lower trench is greater than two times a width of the lower trench. 
 
     
     
       8. The method of  claim 7 , wherein each of the upper trenches has a second length in the second direction and a second width in the first direction, and
 the second width is smaller than the first width. 
 
     
     
       9. The method of  claim 8 , wherein each of the upper trenches has a second depth greater than two times the second width. 
     
     
       10. The method of  claim 6 , further comprising forming a first insulating separation pattern on the substrate to cross the upper portions of the epitaxial layer. 
     
     
       11. The method of  claim 10 , further comprising forming a second insulating separation pattern on the substrate to cross the lower portion of the epitaxial layer and the first insulating separation pattern. 
     
     
       12. The method of  claim 11 , wherein top surfaces of the first and second insulating separation patterns is located at a lower level than the top surfaces of the upper portions. 
     
     
       13. The method of  claim 6 , further comprising recessing a top surface of the mask pattern to partially expose sidewalls of the upper portions before forming the gate structure. 
     
     
       14. The method of  claim 6 , wherein the lower portion comprises crystal defects and the upper portions are substantially free of crystal defects. 
     
     
       15. The method of  claim 6 , wherein the epitaxial layer is a unitary body, in which an interface is not formed between the lower portion and the upper portions. 
     
     
       16. The method of  claim 6 , wherein forming the lower trench comprises:
 etching a portion of the substrate to form a device isolation trench defining a preliminary active pattern; 
 forming the device isolation layer in the device isolation trench; and 
 etching the preliminary active pattern to expose a sidewall of the device isolation layer. 
 
     
     
       17. The method of  claim 6 , further comprising, before forming the gate structure:
 alternatingly stacking first semiconductor layers and second semiconductor layers on the upper portions of the epitaxial layer; and 
 recessing a top surface of the mask pattern to partially expose sidewalls of the first and second semiconductor layers. 
 
     
     
       18. The method of  claim 17 , further comprising, before forming the gate structure:
 forming a plurality of channel patterns stacked on the each of the upper portions and between the source and drain patterns, 
 wherein channel patterns of the plurality of channel patterns are spaced apart from each other on the each of the upper portions in a third direction perpendicular to a plane formed by the first direction and the second direction, and 
 wherein the gate structure comprises a metal gate pattern that extends in the first direction and surrounds the channel patterns. 
 
     
     
       19. The method of  claim 18 , wherein the channel patterns extend parallel to the upper portions.