Pixel driving circuit and liquid crystal display panel

Abstract

The present application provides a pixel driving circuit and a liquid crystal display panel. The pixel driving circuit comprises a main pixel electrode driving module, a sub-pixel electrode driving module, a first potential regulation module, and a second potential regulation module.

What is claimed is: 
     
       1. A pixel driving circuit, comprising:
 a main pixel electrode driving module, receiving a data signal, a scan signal, a first common electrode signal and a second common electrode signal, and electrically connected to a first node, wherein the main pixel electrode driving module is configured to output the data signal to the first node based on the scan signal, the first common electrode signal and the second common electrode signal; 
 a sub-pixel electrode driving module, receiving the data signal, the scan signal, the first common electrode signal and the second common electrode signal, and electrically connected to a second node, wherein the sub-pixel electrode driving module is configured to output the data signal to the second node based on the scan signal, the first common electrode signal and the second common electrode signal; 
 a first potential regulation module, receiving the scan signal and a first electrode signal, and electrically connected to the first node, wherein the first potential regulation module is configured to regulate, under the control of the scan signal, a potential of the first node according to the first electrode signal; and 
 a second potential regulation module, receiving the scan signal and a second electrode signal, and electrically connected to the second node, wherein the second potential regulation module is configured to regulate, under the control of the scan signal, a potential of the second node according to the second electrode signal. 
 
     
     
       2. The pixel driving circuit as claimed in  claim 1 , wherein the main pixel electrode driving module comprises a first transistor, a first liquid crystal capacitor and a first storage capacitor;
 a gate electrode of the first transistor receives the scan signal, one of a source electrode and a drain electrode of the transistor receives the data signal, and the other one of the source electrode and the drain electrode of the transistor is electrically connected to the first node; 
 a first terminal of the first liquid crystal capacitor is electrically connected to the first node, and a second terminal of the first liquid crystal capacitor receives the first common electrode signal; and 
 a first terminal of the first storage capacitor is electrically connected to the first node, and a second terminal of the first storage capacitor receives the second common electrode signal. 
 
     
     
       3. The pixel driving circuit as claimed in  claim 1 , wherein the sub-pixel electrode driving module comprises a second transistor, a second liquid crystal capacitor and a second storage capacitor;
 a gate electrode of the second transistor receives the scan signal, one of a source electrode and a drain electrode of the second transistor receives the data signal, and the other one of the source electrode and the drain electrode of the second transistor is electrically connected to the second node; 
 a first terminal of the second liquid crystal capacitor is electrically connected to the second node, and a second terminal of the second liquid crystal capacitor receives the first common electrode signal; and 
 a first terminal of the second storage capacitor is electrically connected to the second node, and a second terminal of the second storage capacitor receives the second common electrode signal. 
 
     
     
       4. The pixel driving circuit as claimed in  claim 1 , wherein the first potential regulation module comprises a third transistor;
 a gate electrode of the third transistor receives the scan signal, one of a source electrode and a drain electrode of the third transistor is electrically connected to the first node, and the other one of the source electrode and the drain electrode of the third transistor receives the first electrode signal. 
 
     
     
       5. The pixel driving circuit as claimed in  claim 1 , wherein the second potential regulation module comprises a fourth transistor;
 a gate electrode of the fourth transistor receives the scan signal, one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second node, and the other one of the source electrode and the drain electrode of the fourth transistor receives the second electrode signal. 
 
     
     
       6. The pixel driving circuit as claimed in  claim 1 , wherein a potential of the first electrode signal is equal to a potential of the second common electrode signal. 
     
     
       7. The pixel driving circuit as claimed in  claim 1 , wherein a potential of the first electrode signal is not equal to a potential of the second electrode signal. 
     
     
       8. A liquid crystal display panel, comprising:
 a plurality of data lines, wherein each of the data lines is configured to provide a data signal; 
 a plurality of scan lines, wherein each of the scan lines is configured to provide a scan signal; and 
 a plurality of pixel units defined by cross areas of the plurality of the scan lines and the plurality of the data lines, wherein each of the pixel units comprises a pixel driving circuit, comprising: 
 a main pixel electrode driving module, receiving a data signal, a scan signal, a first common electrode signal and a second common electrode signal, and electrically connected to a first node, wherein the main pixel electrode driving module is configured to output the data signal to the first node based on the scan signal, the first common electrode signal and the second common electrode signal; 
 a sub-pixel electrode driving module, receiving the data signal, the scan signal, the first common electrode signal and the second common electrode signal, and electrically connected to a second node, wherein the sub-pixel electrode driving module is configured to output the data signal to the second node based on the scan signal, the first common electrode signal and the second common electrode signal; 
 a first potential regulation module, receiving the scan signal and a first electrode signal, and electrically connected to the first node, wherein the first potential regulation module is configured to regulate, under the control of the scan signal, a potential of the first node according to the first electrode signal; and 
 a second potential regulation module, receiving the scan signal and a second electrode signal, and electrically connected to the second node, wherein the second potential regulation module is configured to regulate, under the control of the scan signal, a potential of the second node according to the second electrode signal. 
 
     
     
       9. The liquid crystal display panel as claimed in  claim 8 , wherein the main pixel electrode driving module comprises a first transistor, a first liquid crystal capacitor and a first storage capacitor;
 a gate electrode of the first transistor receives the scan signal, one of a source electrode and a drain electrode of the transistor receives the data signal, and the other one of the source electrode and the drain electrode of the transistor is electrically connected to the first node; 
 a first terminal of the first liquid crystal capacitor is electrically connected to the first node, and a second terminal of the first liquid crystal capacitor receives the first common electrode signal; and 
 a first terminal of the first storage capacitor is electrically connected to the first node, and a second terminal of the first storage capacitor receives the second common electrode signal. 
 
     
     
       10. The liquid crystal display panel as claimed in  claim 8 , wherein the sub-pixel electrode driving module comprises a second transistor, a second liquid crystal capacitor and a second storage capacitor;
 a gate electrode of the second transistor receives the scan signal, one of a source electrode and a drain electrode of the second transistor receives the data signal, and the other one of the source electrode and the drain electrode of the second transistor is electrically connected to the second node; 
 a first terminal of the second liquid crystal capacitor is electrically connected to the second node, and a second terminal of the second liquid crystal capacitor receives the first common electrode signal; and 
 a first terminal of the second storage capacitor is electrically connected to the second node, and a second terminal of the second storage capacitor receives the second common electrode signal. 
 
     
     
       11. The liquid crystal display panel as claimed in  claim 8 , wherein the first potential regulation module comprises a third transistor;
 a gate electrode of the third transistor receives the scan signal, one of a source electrode and a drain electrode of the third transistor is electrically connected to the first node, and the other one of the source electrode and the drain electrode of the third transistor receives the first electrode signal. 
 
     
     
       12. The liquid crystal display panel as claimed in  claim 8 , wherein the second potential regulation module comprises a fourth transistor;
 a gate electrode of the fourth transistor receives the scan signal, one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second node, and the other one of the source electrode and the drain electrode of the fourth transistor receives the second electrode signal. 
 
     
     
       13. The liquid crystal display panel as claimed in  claim 8 , wherein a potential of the first electrode signal is equal to a potential of the second common electrode signal. 
     
     
       14. The liquid crystal display panel as claimed in  claim 8 , wherein a potential of the first electrode signal is not equal to a potential of the second electrode signal. 
     
     
       15. The liquid crystal display panel as claimed in  claim 8 , wherein the liquid crystal display panel further comprises a Data line Black Matrix Less (DBS) electrode, disposed above the data lines, and configured to provide the first electrode signal to the pixel driving circuits. 
     
     
       16. The liquid crystal display panel as claimed in  claim 8 , wherein the liquid crystal display panel further comprises a shared electrode, disposed below a pixel electrode, and configured to provide a second electrode signal to the pixel driving circuits. 
     
     
       17. A liquid crystal display panel comprising a pixel unit divided into a main pixel region and a sub-pixel region; wherein:
 the main pixel region comprises a first transistor, a third transistor and a main pixel electrode, a gate electrode of the first transistor is connected to a corresponding scan line, one of a source electrode and a drain electrode of the first transistor is connected to a corresponding data line, and the other one of the source electrode and the drain electrode of the first transistor is connected to the main pixel electrode; a gate electrode of the third transistor is connected to a corresponding scan line, one of a source electrode and a drain electrode of the third transistor is connected to the main pixel electrode, and the other one of the source electrode and the drain electrode of the third transistor is connected to a DBS electrode; wherein the main pixel electrode is connected to a first common electrode signal through a first liquid crystal capacitor and is connected to a second common electrode signal through a first storage capacitor; 
 the sub-pixel region comprises a second transistor, a fourth transistor and a sub-pixel electrode, a gate electrode of the second transistor is connected to a corresponding scan line, one of a source electrode and a drain electrode of the second transistor is connected to a corresponding data line, and the other one of the source electrode and the drain electrode of the second transistor is connected to the sub-pixel electrode; a gate electrode of the fourth transistor is connected to a corresponding scan line, one of a source electrode and a drain electrode of the fourth transistor is connected to the sub-pixel electrode, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to a shared electrode; wherein the sub-pixel electrode is connected to the first common electrode signal through a second liquid crystal capacitor and is connected to the second common electrode signal through a second storage capacitor. 
 
     
     
       18. The liquid crystal display panel as claimed in  claim 17 , wherein the DBS electrode is disposed above the data line and configured to provide a first electrode signal, and wherein a potential of the first electrode signal is equal to a potential of second common electrode signal. 
     
     
       19. The liquid crystal display panel as claimed in  claim 18 , wherein the shared electrode is disposed below the pixel electrodes and configured to provide a second electrode signal, and wherein the potential of the first electrode signal is not equal to a potential of the second electrode signal.