Data transmission circuit, data transmission method, and memory

Abstract

The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.

The invention claimed is: 
     
       1. A data transmission circuit, applied to a memory that comprises a data bus and a plurality of memory regions, the data transmission circuit comprising at least two data transmission structures, wherein
 each of the data transmission structures comprises a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal, the memory transmission terminal is configured to connect to the memory region, the bus transmission terminal is configured to connect to the data bus, and the interactive transmission terminal is configured to connect to another data transmission structure; 
 data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal; 
 data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal; 
 data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal; the data inputted from the interactive transmission terminal is data inputted through the bus transmission terminal or the memory transmission terminal of another data transmission structure; and 
 a control module is connected to the data transmission structure and receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal, wherein the input control signal and the output control signal are used for indicating a data transmission path of the data transmission structure. 
 
     
     
       2. The data transmission circuit according to  claim 1 , wherein a signal delay between the input control signal and the output control signal is controlled by the adjustment control signal. 
     
     
       3. The data transmission circuit according to  claim 1 , wherein the data transmission structure comprises:
 an input unit configured to receive at least one input data and the input control signal, and output the input data corresponding to the input control signal based on the input control signal; 
 an output unit configured to receive the input data outputted by the input unit and at least one output control signal, and configured to output the input data based on a valid port represented by the output control signal; and 
 a latch unit, connected to the output unit and configured to latch the input data outputted by the output unit. 
 
     
     
       4. The data transmission circuit according to  claim 3 , wherein the input unit comprises:
 a plurality of input controllers, wherein each of the input controllers corresponds to the memory transmission terminal, the bus transmission terminal, or the interactive transmission terminal; 
 each of the input controllers is configured to receive the input data and the input control signal from the corresponding memory transmission terminal, bus transmission terminal or interactive transmission terminal; and 
 the input controller is configured to turn on a corresponding port based on the input control signal, to output the input data of the corresponding port. 
 
     
     
       5. The data transmission circuit according to  claim 3 , wherein the output unit comprises:
 a plurality of output controllers, wherein each of the output controllers corresponds to the memory transmission terminal, the bus transmission terminal or the interactive transmission terminal; 
 each of the output controllers is configured to receive the input data and the output control signal that are outputted by the input unit of the corresponding memory transmission terminal, bus transmission terminal or interactive transmission terminal; and 
 the output controller is configured to turn on a corresponding port based on the output control signal, to output the input data through the corresponding port. 
 
     
     
       6. The data transmission circuit according to  claim 3 , wherein the latch unit comprises: a first inverter and a second inverter connected end to end, and an input terminal of the first inverter and an output terminal of the second inverter are connected in parallel with an output terminal of the output unit. 
     
     
       7. The data transmission circuit according to  claim 3 , wherein the data transmission structure further comprises:
 an input selection unit configured to receive at least one input control signal, and generate a strobe corresponding to the input control signal, wherein the strobe corresponds to a valid port represented by the input control signal, and a selection delay exists between the strobe and the input control signal; and 
 a trigger unit having a clock terminal connected to the input selection unit, an input terminal connected to the input unit, and an output terminal connected to the output unit, and configured to transmit, based on the strobe, the input data received by the input terminal to the output terminal. 
 
     
     
       8. The data transmission circuit according to  claim 7 , wherein the input selection unit comprises:
 a trigger sub-unit configured to receive at least one input control signal, and generate an indication signal if the input control signal is received; 
 a delay sub-unit, connected to the trigger sub-unit and configured to delay the indication signal; and 
 a conversion sub-unit, connected to the delay sub-unit and configured to convert the delayed indication signal into the strobe. 
 
     
     
       9. The data transmission circuit according to  claim 7 , wherein the trigger unit consists of a D flip-flop. 
     
     
       10. The data transmission circuit according to  claim 7 , wherein the data transmission structure further comprises: an inverter unit, disposed between the trigger unit and the input unit and configured to output the input data or invert and output the input data based on an inversion control signal. 
     
     
       11. The data transmission circuit according to  claim 10 , wherein the inverter unit comprises:
 a flip control sub-unit configured to receive the inversion control signal, and generate a first control signal and a second control signal based on the inversion control signal; and 
 a first selection sub-unit and a second selection sub-unit, which are connected in parallel and have an input terminal configured to receive the input data and an output terminal connected to the trigger unit, wherein 
 the first selection sub-unit is configured to be turned on based on the first control signal, to invert and output the input data; and 
 the second selection sub-unit is configured to be turned on based on the second control signal, to output the input data. 
 
     
     
       12. The data transmission circuit according to  claim 1 , wherein the memory transmission terminal comprises: a first transmission terminal, a second transmission terminal, a third transmission terminal, and a fourth transmission terminal; the bus transmission terminal comprises: a fifth transmission terminal and a sixth transmission terminal; the interactive transmission terminal comprises: a seventh transmission terminal and an eighth transmission terminal; and
 the first transmission terminal and the second transmission terminal are connected to a memory region of the memory different from a memory region to which the third transmission terminal and the fourth transmission terminal are connected; the first transmission terminal and the third transmission terminal are configured to transmit low-bit data; the second transmission terminal and the fourth transmission terminal are configured to transmit high-bit data; the fifth transmission terminal and the sixth transmission terminal are configured to perform interactive data transmission between the data bus and the data transmission structure to which the fifth transmission terminal and the sixth transmission terminal belong; and the seventh transmission terminal and the eighth transmission terminal are configured to perform interactive data transmission between two data transmission structures. 
 
     
     
       13. The data transmission circuit according to  claim 12 , wherein
 the fifth transmission terminal is configured to perform interactive data transmission between the data bus and the data transmission structure to which the fifth transmission terminal belongs; and 
 the sixth transmission terminal is configured to perform one-way data transmission from the data transmission structure, to which the sixth transmission terminal belongs, to the data bus. 
 
     
     
       14. A data transmission method, applied to the data transmission circuit according to  claim 1 , comprising:
 receiving the input control signal and the adjustment control signal; 
 generating the output control signal corresponding to the input control signal based on the input control signal and the adjustment control signal, wherein a signal delay between the input control signal and the output control signal is controlled by the adjustment control signal; 
 obtaining the data transmission path based on the input control signal and the output control signal; and 
 transmitting data based on the data transmission path. 
 
     
     
       15. A memory, adopting the data transmission circuit according to  claim 1 .