Data retention in memory devices

Abstract

A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

What is claimed is: 
     
       1. A method performed by a memory controller, the method comprising:
 accessing a memory page in a memory block of a memory device; 
 determining a number of error bits associated with memory data stored in the memory page; 
 accessing a specified portion of the memory block comprising one or more memory cells storing an erase count for the memory page, the erase count indicating a number of erase operations performed on the memory page, 
 wherein a number of the one or more memory cells storing the erase count corresponds to a maximum number of error bits associated with memory data that can be corrected by the memory controller; 
 obtaining the erase count for the memory page from the specified portion of the memory block; 
 determining, based at least on the obtained erase count for the memory page, an error threshold value for the memory data stored in the memory page; 
 comparing the number of error bits associated with memory data to the error threshold value; 
 in response to the comparing, determining that the number of error bits is greater than or equal to the error threshold value; and 
 upon determining that the number of error bits is greater than or equal to the error threshold value, causing a data refresh for the memory page. 
 
     
     
       2. The method of  claim 1 , wherein causing the data refresh for the memory page comprises:
 setting a flag associated with the memory page to indicate that the memory page is a candidate for a data refresh. 
 
     
     
       3. The method of  claim 2 , further comprising:
 determining, by a host device coupled to the memory device, that the flag associated with the memory page is set; and 
 in response to determining that the flag associated with the memory page is set, performing, by the host device, a data refresh of the memory page. 
 
     
     
       4. The method of  claim 1 , wherein the error threshold value is one of a plurality of error threshold values, each of which corresponds to a different range of erase counts to trigger a data refresh, and
 wherein a higher range of erase counts is associated with a lower error threshold value while a lower range of erase counts is associated with a higher error threshold value. 
 
     
     
       5. The method of  claim 1 , wherein the erase count includes one of a program/erase cycle count, or information indicating an access rate of the memory page. 
     
     
       6. The method of  claim 1 , wherein the specified portion of the memory block storing the erase count for the memory page includes a specified section of the memory page, and wherein accessing the specified portion of the memory block comprises accessing the specified section of the memory page. 
     
     
       7. The method of  claim 1 , wherein the specified portion of the memory block storing the erase count for the memory page includes a section of a different, second memory page. 
     
     
       8. A memory device comprising:
 a memory array including a one or more memory blocks, with at least one memory block including one or more memory pages; and 
 a memory controller configured to perform operations comprising:
 accessing a memory page in a memory block of the one or more memory blocks; 
 determining a number of error bits associated with memory data stored in the memory page; 
 accessing a specified portion of the memory block comprising one or more memory cells storing an erase count for the memory page, the erase count indicating a number of erase operations performed on the memory page, 
 wherein a number of the one or more memory cells storing the erase count corresponds to a maximum number of error bits associated with memory data that can be corrected by the memory controller; 
 obtaining the erase count for the memory page from the specified portion of the memory block; 
 determining, based at least on the obtained erase count for the memory page, an error threshold value for the memory data stored in the memory page; 
 comparing the number of error bits associated with memory data to the error threshold value; 
 in response to the comparing, determining that the number of error bits is greater than or equal to the error threshold value; and 
 upon determining that the number of error bits is greater than or equal to the error threshold value causing a data refresh for the memory page. 
 
 
     
     
       9. The memory device of  claim 8 , wherein the memory controller comprises:
 a decoder configured to determine, based at least on the obtained erase count for the memory page, the error threshold value for the memory data from a plurality of error threshold values, each of which corresponds to a different range of erase counts to trigger a data refresh; and 
 a comparator configured to compare the number of error bits to the error threshold value. 
 
     
     
       10. The memory device of  claim 8 , wherein causing the data refresh for the memory page comprises:
 setting a flag associated with the memory page to indicate that the memory page is a candidate for a data refresh. 
 
     
     
       11. The memory device of  claim 10 , wherein a host device coupled to the memory device is configured to perform a data refresh of the memory page in response to determining that the flag associated with the memory page is set. 
     
     
       12. The memory device of  claim 8 , wherein the erase count includes one of a program/erase cycle count, or information indicating an access rate of the memory page. 
     
     
       13. The memory device of  claim 8 , wherein the specified portion of the memory block storing the erase count for the memory page includes a specified section of the memory page, and wherein accessing the specified portion of the memory block comprises accessing the specified section of the memory page. 
     
     
       14. The memory device of  claim 8 , wherein the specified portion of the memory block storing the erase count for the memory page includes a section of a different, second memory page. 
     
     
       15. A method performed by a memory controller, the method comprising:
 accessing a first memory page in a memory block of a memory device; 
 obtaining a first erase count corresponding to the first memory page, the first erase count indicating a number of erase operations performed on the first memory page; 
 determining, based at least on the first erase count, a first error threshold value of a plurality of error threshold values for first memory data stored in the first memory page, wherein an error threshold value of a plurality of error threshold values indicates a number of error bits in memory data of a memory page to trigger a data refresh for the memory page; 
 accessing a second memory page in the memory block of the memory device; 
 obtaining a second erase count corresponding to the second memory page, the second erase count indicating a number of erase operations performed on the second memory page; and 
 determining, based at least on the second erase count, a second error threshold value for second memory data stored in the second memory page, 
 wherein the second erase count is greater than the first erase count and the second error threshold value is less than the first error threshold value. 
 
     
     
       16. The method of  claim 15 , further comprising:
 determining a first number of error bits associated with the first memory data; 
 comparing the first number of error bits associated to the first error threshold value; 
 in response to the comparing, determining that the first number of error bits is greater than or equal to the first error threshold value; and 
 upon determining that the first number of error bits is greater than or equal to the first error threshold value, causing a data refresh for the first memory page. 
 
     
     
       17. The method of  claim 15 , further comprising:
 determining a second number of error bits associated with the second memory data; 
 comparing the second number of error bits associated to the second error threshold value; 
 in response to the comparing, determining that the second number of error bits is less than the second error threshold value; and 
 upon determining that the second number of error bits is less than the second error threshold value, indicating that the second memory page is not a candidate for a data refresh. 
 
     
     
       18. The method of  claim 15 , wherein obtaining the first erase count corresponding to the first memory page comprises accessing a first portion of the memory block configured to store the first erase count, and
 obtaining the second erase count corresponding to the second memory page comprises accessing a second portion of the memory block configured to store the second erase count, the second portion being different than the first portion.