Method and system of performing convolution in neural networks with variable dilation rate

Abstract

A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.

What is claimed is: 
     
       1. A processor-implemented convolution method in a neural network, by a processor of a computing system, the method comprising:
 receiving, by the processor, an input image including a plurality of pixel values; 
 receiving, by the processor, a size of a first kernel of another neural network and a dilation rate set for the first kernel; 
 generating, by the processor, one or more disintegrated kernels by disintegrating the first kernel into the one or more disintegrated kernels of the neural network; 
 generating, by the processor, one or more feature matrices of the neural network by performing a convolution operation between one or more kernel values of the one or more disintegrated kernels and pixel values corresponding to each block of one or more blocks of the input image; and 
 determining, by the processor, an output image based on a combination of the one or more feature matrices. 
 
     
     
       2. The method of  claim 1 , wherein a size of the one or more blocks of the input image is determined based on at least one of a baseline architecture of a memory associated with the computing system and the dilation rate. 
     
     
       3. The method of  claim 2 , further comprising determining the size of the one or more disintegrated kernels based on at least one of the size of the first kernel, the baseline architecture of the memory, and the dilation rate. 
     
     
       4. The method of  claim 2 , further comprising determining an address of the one or more blocks of the input image corresponding to each of the one or more disintegrated kernels based on the dilation rate and one or more parameters associated with a size of the input image and the memory. 
     
     
       5. The method of  claim 4 , wherein the address of the one or more blocks is determined based on the one or more parameters, wherein the one or more parameters comprise at least one of a Base Address of a first block among the one or more blocks in the memory, a Column Stride, a Cell Number X, a Row Stride, a Cell Number Y, a Channel Stride, a Cell Number Z, a Dilation Column Stride, a Dilation Offset X, a Dilation Row Stride, and a Dilation Offset Y, wherein X is indicative of a number of blocks in a horizontal direction of the image, Y is indicative of a number of blocks in a vertical direction of the image, Z is indicative of a number of blocks per channel in the image. 
     
     
       6. The method of  claim 4 , further comprising fetching the one or more blocks of the input image based on the address and the one or more disintegrated kernels from the memory. 
     
     
       7. The method of  claim 6 , wherein the fetching of the one or more blocks of the input image from the memory comprises fetching a plurality of pixel values of the input image corresponding to each block of the one or more blocks of the input image. 
     
     
       8. The method of  claim 6 , wherein the fetching of the one or more disintegrated kernels from the memory comprises:
 identifying one or more kernel values corresponding to the one or more disintegrated kernels in a second kernel, wherein the second kernel is generated based on the first kernel and the dilation rate; and 
 fetching the one or more kernel values corresponding to the one or more disintegrated kernels based on the size of the one or more disintegrated kernels. 
 
     
     
       9. The method of  claim 8 , wherein the dilation rate is indicative of one or more zeros to be inserted between the one or more kernel values of the first kernel to generate the second kernel, and
 the one or more zeros inserted between the one or more kernel values is equal to one less than the dilation rate. 
 
     
     
       10. The method of  claim 9 , further comprising skipping determining an address of the one or more blocks of the input image to be multiplied with the one or more zeros inserted in the second kernel. 
     
     
       11. A computing system comprising:
 a processor; and 
 a memory communicatively coupled to the processor, wherein the memory stores processor instructions, which, on execution by the processor, configure the processor to:
 receive an input image including a plurality of pixel values; 
 receive a size of a first kernel of another neural network and a dilation rate set for the first kernel; 
 generate one or more disintegrated kernels by disintegrating the first kernel into the one or more disintegrated kernels of neural network; 
 generate one or more feature matrices of the neural network by performing a convolution operation between one or more kernel values of the one or more disintegrated kernels and pixel values corresponding to each block of one or more blocks of the input image; and 
 determine an output image based on a combination of the one or more feature matrices. 
 
 
     
     
       12. The computing system of  claim 11 , wherein a size of the one or more blocks of the input image is determined based on at least one of a baseline architecture of the memory and the dilation rate. 
     
     
       13. The computing system of  claim 12 , wherein the processor is configured to determine the size of the one or more disintegrated kernels based on at least one of the size of the first kernel, the baseline architecture of the memory, and the dilation rate. 
     
     
       14. The computing system of  claim 12 , wherein the processor is configured to determine an address of the one or more blocks of the input image corresponding to each of the one or more disintegrated kernels based on the dilation rate and one or more parameters associated with a size of the input image and the memory. 
     
     
       15. The computing system of  claim 14 , wherein the address of the one or more blocks is determined based on the one or more parameters, wherein the one or more parameters comprise at least one of a Base Address of a first block among the one or more blocks in the memory, a Column Stride, a Cell Number X, a Row Stride, a Cell Number Y, a Channel Stride, a Cell Number Z, a Dilation Column Stride, a Dilation Offset X, a Dilation Row Stride, and a Dilation Offset Y, wherein X is indicative of a number of blocks in a horizontal direction of the image, Y is indicative of a number of blocks in a vertical direction of the image, Z is indicative of a number of blocks per channel in the image. 
     
     
       16. The computing system of  claim 14 , wherein the processor is further configured to fetch the one or more blocks of the input image based on the address, and the one or more disintegrated kernels from the memory. 
     
     
       17. The computing system of  claim 16 , wherein the fetching of the one or more blocks of the input image by the processor comprises fetching a plurality of pixel values of the input image corresponding to each block of the one or more blocks of the input image. 
     
     
       18. The computing system of  claim 16 , wherein the fetching of the one or more disintegrated kernels from the memory by the processor comprises:
 identifying one or more kernel values corresponding to the one or more disintegrated kernels in a second kernel, wherein the second kernel is generated based on the first kernel and the dilation rate; and 
 fetching the one or more kernel values corresponding to the one or more disintegrated kernels based on the size of the one or more disintegrated kernels. 
 
     
     
       19. The computing system of  claim 18 , wherein the dilation rate is indicative of one or more zeros to be inserted between the one or more kernel values of the first kernel to generate the second kernel, and
 the one or more zeros inserted between the one or more kernel values is equal to one less than the dilation rate. 
 
     
     
       20. The computing system of  claim 19 , wherein the processor is further configured to skip determining an address of the one or more blocks of the input image to be multiplied with the one or more zeros inserted in the second kernel.