Signal processing system capable of performing voltage and frequency calibration

Abstract

A signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit. The power management unit provides a first voltage to the digital signal processing circuit. When in a calibration mode the digital control circuit controls the power management unit to set the first voltage at a minimum preset value, controls the digital signal processing circuit to operate under a first calibration target frequency, triggers the digital signal processing circuit to perform a built-in self-test, raises the first voltage when the built-in self-test fails, triggers the digital signal processing circuit to perform the built-in self-test again, and stores the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to a non-volatile memory when the built-in self-test has succeeded.

What is claimed is: 
     
       1. A signal processing system comprising:
 a digital signal processing circuit; 
 a power management unit coupled to the digital signal processing circuit and configured to provide a first voltage to the digital signal processing circuit; and 
 a digital control circuit coupled to the digital signal processing circuit and the power management unit, and comprising a non-volatile memory, the digital control circuit being configured to, when in a calibration mode:
 control the power management unit to set the first voltage at a minimum preset value; 
 control the digital signal processing circuit to operate under a first calibration target frequency; 
 trigger the digital signal processing circuit to perform a built-in self-test; 
 raise the first voltage when the built-in self-test fails; 
 trigger the digital signal processing circuit to perform the built-in self-test again; and 
 store the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to the non-volatile memory when the built-in self-test has succeeded. 
 
 
     
     
       2. The signal processing system of  claim 1 , wherein the digital control circuit is further configured to, when in an application mode:
 read a calibrated value of the first voltage corresponding to an application target frequency from the non-volatile memory; 
 control the power management unit to set the first voltage at the calibrated value; and 
 control the digital signal processing circuit to operate under the application target frequency. 
 
     
     
       3. The signal processing system of  claim 1 , wherein the digital control circuit further comprises:
 a first control unit coupled to the digital signal processing circuit and the power management unit, and configure to output a voltage control signal to the power management unit to adjust the first voltage, output a frequency control signal to a clock generator of the digital signal processing circuit to control an operating frequency of the digital signal processing circuit, and determine a result of the built-in self-test; and 
 a second control unit coupled to the first control unit, and configured to have the first control unit enter the calibration mode and set the first calibration target frequency corresponding to the calibration mode according to a first system instruction, and have the first control unit enter an application mode and set an application target frequency corresponding to the application mode. 
 
     
     
       4. The signal processing system of  claim 1 , wherein the power management unit is further configured to provide a second voltage to the digital control circuit as a power supply. 
     
     
       5. The signal processing system of  claim 1 , wherein the digital signal processing circuit further comprises a digital signal processor comprising an internal dynamic random access memory and a first built-in self-test unit, wherein:
 the first built-in self-test unit is coupled to the internal dynamic random access memory; and 
 the digital signal processing circuit at least triggers the first built-in self-test unit to perform the built-in self-test. 
 
     
     
       6. The signal processing system of  claim 5 , wherein the digital signal processing circuit further comprises a static random access memory and a second built-in self-test unit, wherein:
 the second built-in self-test unit is coupled to the static random access memory; and 
 the digital signal processing circuit triggers the first built-in self-test unit and the second built-in self-test unit to perform the built-in self-test. 
 
     
     
       7. The signal processing system of  claim 1 , wherein the non-volatile memory is a one-time programmable (OTP) non-volatile memory. 
     
     
       8. The signal processing system of  claim 1 , wherein the digital control circuit is further configured to, after the first calibration target frequency and the value of the first voltage corresponding to the first calibration target frequency are stored to the non-volatile memory in the calibration mode:
 control the power management unit to set the first voltage at the minimum preset value; 
 control the digital signal processing circuit to operate under a second calibration target frequency; 
 trigger the digital signal processing circuit to perform the built-in self-test; 
 raise the first voltage when the built-in self-test fails; 
 trigger the digital signal processing circuit to perform the built-in self-test again; and 
 store the second calibration target frequency and a value of the first voltage corresponding to the second calibration target frequency to the non-volatile memory when the built-in self-test has succeeded. 
 
     
     
       9. A method for operating a signal processing system, the signal processing system comprising a digital signal processing circuit, a power management unit, and a digital control circuit comprising a non-volatile memory, the method comprising, in a calibration mode:
 the digital control circuit controlling the power management unit to output a first voltage at a minimum preset value to the digital signal processing circuit; 
 the digital control circuit controlling the digital signal processing circuit to operate under a first calibration target frequency; 
 the digital control circuit triggering the digital signal processing circuit to perform a built-in self-test; 
 the digital control circuit controlling the power management unit to raise the first voltage when the built-in self-test fails; 
 the digital control circuit triggering the digital signal processing circuit to perform the built-in self-test again; and 
 the digital control circuit storing the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to the non-volatile memory when the built-in self-test has succeeded. 
 
     
     
       10. The method of  claim 9  further comprising, in an application mode:
 the digital control circuit reading a calibrated value of the first voltage corresponding to an application target frequency from the non-volatile memory; 
 the digital control circuit controlling the power management unit to set the first voltage at the calibrated value; and 
 the digital control circuit controlling the digital signal processing circuit to operate under the application target frequency. 
 
     
     
       11. The method of  claim 9 , further comprising the power management unit providing a second voltage to the digital control circuit as a power supply. 
     
     
       12. The method of  claim 9 , wherein:
 the digital signal processing circuit further comprises a digital signal processor comprising an internal dynamic random access memory and a first built-in self-test unit, the first built-in self-test unit being coupled to the internal dynamic random access memory; and 
 the digital control circuit triggering the digital signal processing circuit to perform the built-in self-test comprises the digital signal processing circuit triggering the first built-in self-test unit. 
 
     
     
       13. The method of  claim 12 , wherein:
 the digital signal processing circuit further comprises a static random access memory and a second built-in self-test unit, and the second built-in self-test unit being coupled to the static random access memory; and 
 the digital control circuit triggering the digital signal processing circuit to perform the built-in self-test comprises the digital signal processing circuit triggering the first built-in self-test unit and the second built-in self-test unit. 
 
     
     
       14. The method of  claim 9 , wherein the non-volatile memory is a one-time programmable (OTP) non-volatile memory. 
     
     
       15. The method of  claim 9  further comprising in the calibration mode, after the digital control circuit stores the first calibration target frequency and the value of the first voltage corresponding to the first calibration target frequency to the non-volatile memory:
 the digital control circuit controlling the power management unit to set the first voltage at the minimum preset value; 
 the digital control circuit controlling the digital signal processing circuit to operate under a second calibration target frequency; 
 the digital control circuit triggering the digital signal processing circuit to perform the built-in self-test; 
 the digital control circuit controlling the power management unit to raise the first voltage when the built-in self-test fails; 
 the digital control circuit triggering the digital signal processing circuit to perform the built-in self-test again; and 
 the digital control circuit storing the second calibration target frequency and a value of the first voltage corresponding to the second calibration target frequency to the non-volatile memory when the built-in self-test has succeeded.