Non-volatile memory device including signal lines arranged at the same level as a common source line and a gate arranged at the same level as a ground selection line

Abstract

A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

What is claimed is: 
     
       1. A non-volatile memory device, comprising:
 a memory cell array including: 
 a plurality of wordlines extended in a first direction and stacked in a vertical direction, 
 a plurality of channel structures extending in the vertical direction, 
 a ground selection line below the plurality of wordlines in the vertical direction, and 
 a common source line below the ground selection line in the vertical direction; and 
 a plurality of pass transistors respectively connected to a plurality of signal lines and commonly connected to a gate extending in the first direction, 
 wherein the plurality of signal lines and the common source line are arranged at the same level along the first direction and extend in a second direction perpendicular to the first direction, and 
 wherein the gate is arranged at the same level as the ground selection line. 
 
     
     
       2. The non-volatile memory device of  claim 1 , wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of the plurality of signal lines and a first wordline of the plurality of wordlines,
 wherein the first pass transistor includes a channel extending in the vertical direction from the first signal line through the gate, and 
 wherein a width of the channel between the gate and the first wordline is greater than a width of the channel below the gate. 
 
     
     
       3. The non-volatile memory device of  claim 1 , wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of the plurality of signal lines and a first wordline of the plurality of wordlines,
 wherein the first pass transistor is a vertical pass transistor, and 
 wherein each of the plurality of pass transistors includes a vertical channel, wherein tops of the vertical channels are below the first wordline. 
 
     
     
       4. The non-volatile memory device of  claim 1 , wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of the plurality of signal lines and a first wordline of the plurality of wordlines, and
 wherein a first channel structure of the plurality of channel structures has a first width at an area between the ground selection line and the first wordline, the channel of the first pass transistor has a second width at an area between the gate and the first wordline, the second width being greater than the first width. 
 
     
     
       5. The non-volatile memory device of  claim 4 , wherein each of the plurality of pass transistors includes a vertical channel,
 wherein tops of the vertical channels are at the same level as each other, and 
 wherein the second width is at least two times the first width. 
 
     
     
       6. The non-volatile memory device of  claim 1 , wherein the plurality of pass transistors are formed in an area where the plurality of wordlines form a staircase shape. 
     
     
       7. The non-volatile memory device of  claim 1 , further comprising:
 a row decoder including a transistor electrically connected to a first pass transistor of the plurality of pass transistors. 
 
     
     
       8. The non-volatile memory device of  claim 7 , wherein the memory cell array and the plurality of pass transistors are disposed in a first semiconductor layer,
 wherein the row decoder is disposed in a second semiconductor layer, and 
 wherein the first semiconductor layer is stacked on the second semiconductor layer in the second direction. 
 
     
     
       9. The non-volatile memory device of  claim 1 , wherein the plurality of pass transistors are provided with the same block selection signal. 
     
     
       10. A non-volatile memory device, comprising:
 a first semiconductor layer including a memory cell array and a plurality of pass transistors, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a vertical direction; and 
 a second semiconductor layer disposed below the first semiconductor layer in the vertical direction, 
 wherein the memory cell array further includes a plurality of channel structures extending in the vertical direction, a ground selection line below the plurality of wordlines in the vertical direction, and a common source line below the ground selection line in the vertical direction, 
 wherein the plurality of pass transistors are respectively connected to a plurality of signal lines and commonly connected to a gate extending in the first direction, 
 wherein the plurality of signal lines and the common source line are arranged at the same level along the first direction and extend in a second direction perpendicular to the first direction, and 
 wherein the gate is arranged at the same level as the ground selection line. 
 
     
     
       11. The non-volatile memory device of  claim 10 , wherein the second semiconductor layer includes a transistor electrically connected to a first pass transistor of the plurality of pass transistors, and
 wherein the transistor is included in a row decoder. 
 
     
     
       12. The non-volatile memory device of  claim 11 , wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of the plurality of signal lines and a first wordline of the plurality of wordlines. 
     
     
       13. The non-volatile memory device of  claim 12 , wherein the first pass transistor includes a channel extending in the vertical direction from the first signal line through the gate, and
 wherein a width of the channel between the gate and the first wordline is greater than a width of the channel below the gate. 
 
     
     
       14. The non-volatile memory device of  claim 12 , wherein the first pass transistor is a vertical pass transistor, and
 wherein each of the plurality of pass transistors includes a vertical channel, wherein tops of the vertical channels are below the first wordline. 
 
     
     
       15. The non-volatile memory device of  claim 12 , wherein a first channel structure of the plurality of channel structures has a first width at an area between the ground selection line and the first wordline, the channel of the first pass transistor has a second width at an area between the gate and the first wordline, the second width being greater than the first width. 
     
     
       16. The non-volatile memory device of  claim 10 , wherein the plurality of pass transistors are formed in an area where the plurality of wordlines form a staircase shape. 
     
     
       17. The non-volatile memory device of  claim 10 , wherein the plurality of pass transistors are provided with the same block selection signal. 
     
     
       18. A non-volatile memory device, comprising:
 a memory cell region including a memory cell array, a plurality of pass transistors, and a first metal pad; and 
 a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, 
 wherein the memory cell array includes: 
 a plurality of wordlines extended in a first direction and stacked in a vertical direction, 
 a plurality of channel structures extending in the vertical direction, 
 a ground selection line below the plurality of wordlines in the vertical direction, and 
 a common source line below the ground selection line in the vertical direction, 
 wherein the plurality of pass transistors are respectively connected to a plurality of signal lines and commonly connected to a gate extending in the first direction, 
 wherein the plurality of signal lines and the common source line are arranged at the same level along the first direction and extend in a second direction perpendicular to the first direction, and 
 wherein the gate is arranged at the same level as the ground selection line. 
 
     
     
       19. The non-volatile memory device of  claim 18 , wherein the peripheral circuit region further includes a transistor electrically connected to a first pass transistor of the plurality of pass transistors, and
 wherein the transistor is included in a row decoder. 
 
     
     
       20. The non-volatile memory device of  claim 18 , wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines,
 wherein the first pass transistor includes a channel extending in the vertical direction from the first signal line through the gate, 
 wherein a width of the channel between the gate and the first wordline is greater than a width of the channel below the gate, and 
 wherein a first channel structure of the plurality of channel structures has a first width at an area between the ground selection line and the first wordline, the channel of the first pass transistor has a second width at an area between the gate and the first wordline, the second width being greater than the first width.