Controller, storage device and operation method of the storage device

Abstract

A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.

What is claimed is: 
     
       1. A controller for controlling a memory device including a first memory region and a second memory region having a first bit-density and a second bit density, respectively, comprising:
 a memory storing a logical address list including a number of received logical addresses; 
 a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into the logical address list; 
 a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of the received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; 
 a pattern detection circuit configured to determine a repeatability index of the received logical addresses included in the logical address list; and 
 a parameter adjustment circuit configured to decrease a magnitude of the decay factor based on the repeatability index, to upwardly adjust the weights of the received logical addresses, 
 wherein the CPU is further configured to control the memory device to store the data in the first memory region or the second memory region based on the hotness of the latest received logical address. 
 
     
     
       2. The controller of  claim 1 , wherein the parameter adjustment circuit is configured to increase a size of the logical address list, and decrease the magnitude of the decay factor determined based on the size of the logical address list and the maximum weight. 
     
     
       3. The controller of  claim 1 , wherein the pattern detection circuit is configured to determine the repeatability index such that the repeatability index has a higher value, as diversities of the received logical addresses included in the logical address list lower. 
     
     
       4. The controller of  claim 1 , wherein the pattern detection circuit is configured to determine the repeatability index such that the repeatability index has a higher value, as a receiving cycle of each of the received logical addresses included in the logical address list shortens. 
     
     
       5. The controller of  claim 1 , wherein the parameter adjustment circuit is configured to upwardly adjust the weights of the received logical addresses included in the logical address list, when the repeatability index is equal to or higher than a threshold value. 
     
     
       6. The controller of  claim 5 , wherein the parameter adjustment circuit is configured to maintain or restore the weights of the received logical addresses included in the logical address list to their original values, in response to the repeatability index being lower than the threshold value. 
     
     
       7. The controller of  claim 1 , wherein the second bit-density of the second memory region is higher than the first bit-density of the first memory region, and
 the CPU is configured to control the memory device to store the data in the first memory region, in response to the hotness of the latest received logical address being equal to or higher than a threshold value. 
 
     
     
       8. The controller of  claim 7 , wherein
 the first memory region is a single level cell (SLC) memory region, and 
 the second memory region is a triple level cell (TLC) memory region or a quadruple level cell (QLC) memory region. 
 
     
     
       9. A method of operating a storage device including a first memory region and a second memory region having different bit-densities, comprising:
 receiving a write command, a latest received logical address, and data from a host; 
 inserting the latest received logical address into a logical address list including a number of received logical addresses; 
 determining a repeatability index of the received logical addresses inserted into the logical address list; 
 adjusting weights of the received logical addresses included in the logical address list based on the repeatability index; 
 summing the weights of the received logical addresses having values, equal to a value of the latest received logical address, according to the adjusted weights to determine hotness of the latest received logical address; and 
 storing the data in the first memory region or the second memory region based on the hotness of the latest received logical address. 
 
     
     
       10. The method of  claim 9 , wherein the adjusting the weights of the received logical addresses included in the logical address list based on the repeatability index comprises:
 adjusting a magnitude of a decay factor; and 
 assigning a maximum weight to the latest received logical address and decreasing the weights of the received logical addresses included in the logical address list by the decay factor. 
 
     
     
       11. The method of  claim 10 , wherein the determining the repeatability index comprises determining the repeatability index such that the repeatability index has a higher value, as diversities of the received logical addresses included in the logical address list lowers. 
     
     
       12. The method of  claim 10 , wherein the determining the repeatability index comprises determining the repeatability index such that the repeatability index has a higher value, as an interval at which each of the received logical addresses included in the logical address list is received shortens. 
     
     
       13. The method of  claim 10 , wherein the adjusting the magnitude of the decay factor comprises decreasing the magnitude of the decay factor, in response to the repeatability index being higher than a threshold value. 
     
     
       14. A storage device comprising:
 a memory device including a plurality of memory regions having different respective bit-densities; and 
 a controller configured to
 receive a write command, data, and a latest received logical address from a host, 
 determine hotness of the latest received logical address, based on a number of times of which logical addresses having values, equal to a value of the latest received logical address are received, and weights of the received logical addresses, and 
 store the data in any one of the plurality of memory regions, based on the hotness of the latest received logical address, 
 
 wherein the controller is further configured to determine a repeatability index based on a workload pattern of the host, and upwardly adjust the weights of the received logical addresses based on the repeatability index. 
 
     
     
       15. The storage device of  claim 14 , wherein the controller is configured to
 insert the latest received logical address into a logical address list including a number of received logical addresses, 
 assign a maximum weight to the latest received logical address, 
 decrease weights of the received logical addresses included in the logical address list by a decay factor, and 
 sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine the hotness of the latest received logical address. 
 
     
     
       16. The storage device of  claim 15 , wherein the controller decreases a magnitude of the decay factor, in response to the repeatability index being equal to or higher than a threshold value, to upwardly adjust the weights. 
     
     
       17. The storage device of  claim 15 , wherein the controller is configured to increase a size of the logical address list, in response to the repeatability index being equal to or higher than a threshold value, and adjust the decay factor based on the size of the logical address list and the maximum weight, to upwardly adjust the weights. 
     
     
       18. The storage device of  claim 15 , wherein the controller is configured to determine the repeatability index based on diversities of the received logical addresses included in the logical address list. 
     
     
       19. The storage device of  claim 15 , wherein the controller is configured to determine the repeatability index based on an interval at which each of the received logical addresses included in the logical address list is repeatedly received. 
     
     
       20. The storage device of  claim 14 , wherein the plurality of memory regions include a first memory region having a lowest bit-density, a second memory region having a medium bit-density, and a third memory region having a highest bit-density, and
 the controller is configured to
 store the data in the first memory region in response to the hotness of the latest received logical address being equal to or greater than a first threshold, 
 store the data in the second memory region when the hotness of the latest received logical address is less than the first threshold and equal to or greater than a second threshold, and 
 store the data in the third memory region when the hotness of the latest received logical address is less than the second threshold value.