US11887212B2ActiveUtilityA1
Sparse rendering in computer graphics
Est. expiryFeb 1, 2036(~9.6 yrs left)· nominal 20-yr term from priority
G06T 15/04G06T 11/40G06T 1/60G06T 1/20G06T 15/005G06T 17/10G06T 15/10G06T 15/60G06T 2215/12
77
PatentIndex Score
0
Cited by
28
References
16
Claims
Abstract
A graphics processing system includes a tiling unit configured to tile a scene into a plurality of tiles. A processing unit identifies tiles of the plurality of tiles that are each associated with at least a predetermined number of primitives. A memory management unit allocates a portion of memory to each of the identified tiles and does not allocate a portion of memory for each of the plurality of tiles that are not identified by the processing unit. A rendering unit renders each of the identified tiles and does not render tiles that are not identified by the processing unit.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A graphics processing system comprising:
a tiling unit configured to tile a scene into a plurality of tiles;
a processing unit configured to identify tiles of the plurality of tiles that are each associated with at least a predetermined number of primitives;
a memory management unit configured to allocate a portion of memory to each of the identified tiles and to not allocate a portion of memory for each of the plurality of tiles that are not identified by the processing unit; and
a rendering unit configured to render each of the identified tiles and not render tiles that are not identified by the processing unit.
2. The system as claimed in claim 1 , wherein the processing unit is configured to identify tiles of the plurality of tiles each associated with at least a predetermined number of primitives in dependence on a list of primitives associated with each tile.
3. The system as claimed in claim 1 , wherein the rendering unit is configured to store data resulting from the render of each identified tile at the allocated portion of memory for that tile.
4. The system as claimed in claim 1 , wherein the rendering unit is further configured to, for a subsequent render, access memory locations associated with the tiles that are not identified and the memory management unit is further configured to return a predefined value in response to the access.
5. The system as claimed in claim 1 , wherein the number of tiles identified is less than the number of tiles the scene is tiled into.
6. The system as claimed in claim 1 , wherein the tiling unit is configured to generate a list of primitives associated with each tile by determining which primitives are located at least partially within that tile and the processing unit is configured to identify tiles of the plurality of tiles each associated with at least a predetermined number of primitives in dependence on the list.
7. The system as claimed in claim 1 , wherein the scene is tiled from a first view, and the identified tiles form a first subset of the tiles in the scene, and wherein:
the processing unit is configured to identify a second subset of the tiles that are associated with parts of the scene that are visible in a second view; and
the rendering unit is configured to render each of the tiles that are identified in both the first and second subset.
8. The system as claimed in claim 1 , wherein the scene is tiled from a first view, and the identified tiles form a first subset of the tiles in the scene, and wherein:
the processing unit is configured to identify a second subset of the tiles that are associated with parts of the scene that are visible in a second view; and
the memory management unit is configured to allocate a portion of memory to each of the tiles identified in both the first and second subset.
9. The system as claimed in claim 1 , wherein the rendering unit renders to a texture.
10. The system as claimed in claim 9 , wherein the rendering unit is configured to apply the texture to the scene in a subsequent render of the scene.
11. The system as claimed in claim 10 , wherein the texture is applied to a second view of the scene, the second view being different to the first view.
12. The system as claimed in claim 9 , wherein the texture is a shadow map.
13. The system as claimed in claim 1 , wherein the predetermined number is equal to or greater than one.
14. The system as claimed in claim 1 , wherein the memory management unit is configured to allocate a portion of the memory to each of the identified tiles prior to rendering, and not allocate a portion of memory for each of the plurality of tiles that are not identified by the processing unit prior to rendering.
15. A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the manufacturing system to manufacture a graphics processing system comprising:
a tiling unit configured to tile a scene into a plurality of tiles;
a processing unit configured to identify tiles of the plurality of tiles that are each associated with at least a predetermined number of primitives;
a memory management unit configured to allocate a portion of memory to each of the identified tiles and to not allocate a portion of memory for each of the plurality of tiles that are not identified by the processing unit; and
a rendering unit configured to render each of the identified tiles and not render tiles that are not identified by the processing unit.
16. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform a graphics processing method comprising:
tiling a scene into a plurality of tiles;
identifying tiles that are each associated with at least a predetermined number of primitives;
allocating a portion of memory to each of the identified tiles and not allocating a portion of memory for each of the plurality of tiles that are not identified by the processing unit;
rendering each of the identified tiles and not rendering tiles that are not identified.Cited by (0)
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