Shift register, gate drive circuit and drive method thereof

Abstract

A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

What is claimed is: 
     
       1. A drive method of a gate drive circuit, the gate drive circuit including at least two cascaded shift registers, each register including a pull-up node, a first pull-down node, an input sub-circuit, a first noise reduction sub-circuit and a first pull-down sub-circuit, the first noise reduction sub-circuit being coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, the input sub-circuit being coupled to the pull-up node and a signal input terminal, the first pull-down sub-circuit being coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, the drive method comprising:
 a noise reduction phase and a charging phase included in a frame period for each shift register in the gate drive circuit, wherein the noise reduction phase including:
 transmitting, by the first noise reduction sub-circuit, a first voltage signal received at the first voltage signal terminal to the pull-up node after the first noise reduction sub-circuit is turned on under control of a voltage of the first pull-down node; 
 
 the charging phase including:
 transmitting, by the input sub-circuit, an input signal received at the signal input terminal to the pull-up node after the input sub-circuit is turned on under control of the input signal transmitted by the signal input terminal; 
 transmitting, by the first pull-down sub-circuit, the first voltage signal received at the first voltage signal terminal to the first pull-down node after the first pull-down sub-circuit is turned on under the control of the input signal; and 
 stopping transmitting, by the first noise reduction sub-circuit, the first voltage signal received at the first voltage signal terminal to the pull-up node after the first noise reduction sub-circuit is turned off under the control of the voltage of the first voltage signal transmitted to the first pull-down node, wherein the method further comprises: 
 an operation of raising gate scanning signals output by all shift registers included in the gate drive circuit before a display apparatus to which the gate drive circuit is applied is shut down, wherein the shift register further includes a reset sub-circuit, an initialization sub-circuit, a first pull-down control sub-circuit, a first output sub-circuit, a second noise reduction sub-circuit, a second output sub-circuit and a fifth noise reduction sub-circuit the reset sub-circuit is coupled to the pull-up node, the first voltage signal terminal and a reset signal terminal; 
 the initialization sub-circuit is coupled to the pull-up node, an initialization signal terminal and the first voltage signal terminal; 
 the first pull-down control sub-circuit is coupled to the first voltage signal terminal, a second voltage signal terminal, the pull-up node and the first pull-down node; 
 the first output sub-circuit is coupled to a clock signal terminal, the pull-up node and a first signal output terminal; 
 the second noise reduction sub-circuit is coupled to the first pull-down node, a third voltage signal terminal and the first signal output terminal; 
 the second output sub-circuit is coupled to the pull-up node, the clock signal terminal and a second signal output terminal; and 
 the fifth noise reduction sub-circuit is coupled to the first pull-down node, the first voltage signal terminal and the second signal output terminal; 
 
 wherein a signal input terminal of a first-stage shift register is coupled to a start signal terminal; 
 a signal input terminal of an any-stage shift register except the first-stage shift register is coupled to a second signal output terminal of a previous-stage shift register of the any-stage shift register; 
 a reset signal terminal of an any-stage shift register except a last-stage shift register is coupled to a second signal output terminal of a next-stage shift register of the any-stage shift register; 
 a reset signal terminal of the last-stage shift register is coupled to a signal terminal separately provided for outputting a reset signal, or is coupled to the start signal terminal; and 
 a first signal output terminal of each shifter register is coupled to a single gate line; 
 wherein the operation of raising the gate scanning signals output by all shift registers included in the gate drive circuit, includes:
 pulling down the first voltage signal output by the first voltage signal terminal and a start signal output by the start signal terminal to ground, and raising an initialization signal output by the initialization signal terminal, a second voltage signal output by the second voltage signal terminal, a third voltage signal output by the third voltage signal terminal and a clock signal output by the clock signal terminal, so that the initialization sub-circuit is turned on under control of the initialization signal, and the initialization sub-circuit transmits the first voltage signal to the pull-up node after, such that a voltage of the pull-up node is a grounding voltage;
 the first pull-down control sub-circuit transmits the second voltage signal to the first pull-down node in response to the second voltage signal and the grounding voltage of the pull-up node, such that a voltage of the first pull-down node is raised; 
 the second noise reduction sub-circuit is turned on under control of the voltage of the first pull-down node, and the second noise reduction sub-circuit transmits the third voltage signal to the first signal output terminal, such that a voltage of a gate scanning signal output by the first signal output terminal is raised: 
 the first noise reduction sub-circuit is turned on under the control of the voltage of the first pull-down node, and the first noise reduction sub-circuit transmits the first voltage signal to the pull-up node, such that the voltage of the pull-up node is the grounding voltage; and 
 the fifth noise reduction sub-circuit is turned on under the control of the voltage of the first pull-down node, and the fifth noise reduction sub-circuit transmits the first voltage signal to the second signal output terminal, such that a voltage of a signal output by the second signal output terminal is the grounding voltage; or 
 
 
 wherein the operation of raising the gate scanning signals output by all shift registers included in the gate drive circuit, includes:
 pulling down the first voltage signal output by the first voltage signal terminal, a start signal output by the start signal terminal and an initialization signal output by the initialization signal terminal to ground, and raising a second voltage signal output by the second voltage signal terminal, a third voltage signal output by the third voltage signal terminal and a clock signal output by the clock signal terminal, so that the initialization sub-circuit is turned off under control of the initialization signal, the first pull-down control sub-circuit transmits the second voltage signal to the first pull-down node in response to the second voltage signal and a voltage of the pull-up node, such that a voltage of the first pull-down node is raised; 
 the second noise reduction sub-circuit is turned on under control of the voltage of the first pull-down node, and the second noise reduction sub-circuit transmits the third voltage signal to a first signal output terminal, such that a voltage of a gate scanning signal output by the first signal output terminal is raised; 
 the first noise reduction sub-circuit is turned on under the control of the voltage of the first pull-down node, and the first noise reduction sub-circuit transmits the first voltage signal to the pull-up node, such that the voltage of the pull-up node is the grounding voltage; and 
 the fifth noise reduction sub-circuit is turned on under the control of the voltage of the first pull-down node, and the fifth noise reduction sub-circuit transmits the first voltage signal to the second signal output terminal, such that a voltage of a signal output by the second signal output terminal is the grounding voltage. 
 
 
     
     
       2. A gate drive circuit driven by the method according to  claim 1 , the gate drive circuit including at least two cascaded shift registers, each shift register, comprising the pull-up node, the first pull-down node, the input sub-circuit, the first noise reduction sub-circuit, the first pull-down sub-circuit, the reset sub-circuit, the initialization sub-circuit, the first pull-down control sub-circuit, the first output sub-circuit, the second noise reduction sub-circuit, the second output sub-circuit and the fifth noise reduction sub-circuit,
 wherein the first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and the first voltage signal terminal; 
 the first noise reduction sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the pull-up node under the control of the voltage of the first pull-down node; 
 the input sub-circuit is coupled to the pull-up node and the signal input terminal; the input sub-circuit is configured to transmit the input signal to the pull-up node in response to the input signal received at the signal input terminal; 
 the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal; the first pull-down sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the first pull-down node in response to the input signal received at the signal input terminal, so that the first noise reduction sub-circuit is turned off under the control of the voltage of the first voltage signal transmitted to the first pull-down node to stop transmitting the first voltage signal to the pull-up node; 
 the reset sub-circuit is coupled to the pull-up node, the first voltage signal terminal and the reset signal terminal; the reset sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the pull-up node in response to the reset signal received at the reset signal terminal; 
 the initialization sub-circuit is coupled to the pull-up node, the initialization signal terminal and the first voltage signal terminal; the initialization sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the pull-up node in response to the initialization signal received at the initialization signal terminal; 
 the first pull-down control sub-circuit is coupled to the first voltage signal terminal, the second voltage signal terminal, the pull-up node and the first pull-down node; and 
 the first pull-down control sub-circuit is configured to: transmit the second voltage signal received at the second voltage signal terminal to the first pull-down node in response to the second voltage signal received at the second voltage signal terminal and the voltage of the first voltage signal transmitted to the pull-up node; and 
 transmit the first voltage signal received at the first voltage signal terminal to the first pull-down node in response to the second voltage signal received at the second voltage signal terminal and a voltage of the input signal transmitted to the pull-up node; 
 the first output sub-circuit is coupled to the clock signal terminal, the pull-up node and the first signal output terminal; and 
 the first output sub-circuit is configured to transmit the clock signal received at the clock signal terminal to the first signal output terminal under control of the voltage of the input signal transmitted to the pull-up node; 
 the second noise reduction sub-circuit is coupled to the first pull-down node, the third voltage signal terminal and the first signal output terminal; and 
 the second noise reduction sub-circuit is configured to transmit the third voltage signal received at the third voltage signal terminal to the first signal output terminal under the control of the voltage of the first pull-down node; 
 the second output sub-circuit is coupled to the pull-up node, the clock signal terminal and the second signal output terminal; and 
 the second output sub-circuit is configured to transmit the clock signal received at the clock signal terminal to the second signal output terminal under the control of the voltage of the input signal transmitted to the pull-up node; and 
 the fifth noise reduction sub-circuit is coupled to the first pull-down node, the first voltage signal terminal and the second signal output terminal; and 
 the fifth noise reduction sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the second signal output terminal under the control of the voltage of the first pull-down node. 
 
     
     
       3. The gate drive circuit according to  claim 2 , wherein the first noise reduction sub-circuit includes a first transistor, a control electrode of the first transistor is coupled to the first pull-down node, a first electrode of the first transistor is coupled to the first voltage signal terminal, and a second electrode of the first transistor is coupled to the pull-up node;
 the input sub-circuit includes a second transistor, a control electrode of the second transistor is coupled to the signal input terminal, a first electrode of the second transistor is coupled to the signal input terminal, and a second electrode of the second transistor is coupled to the pull-up node; and 
 the first pull-down sub-circuit includes a third transistor, a control electrode of the third transistor is coupled to the signal input terminal, a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the first pull-down node. 
 
     
     
       4. The gate drive circuit according to  claim 2 , wherein the first pull-down control sub-circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first control node;
 a control electrode of the fourth transistor is coupled to the second voltage signal terminal, a first electrode of the fourth transistor is coupled to the second voltage signal terminal, and a second electrode of the fourth transistor is coupled to the first control node; 
 a control electrode of the fifth transistor is coupled to the pull-up node, a first electrode of the fifth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifth transistor is coupled to the first control node; 
 a control electrode of the sixth transistor is coupled to the first control node, a first electrode of the sixth transistor is coupled to the second voltage signal terminal, and a second electrode of the sixth transistor is coupled to the first pull-down node; and 
 a control electrode of the seventh transistor is coupled to the pull-up node, a first electrode of the seventh transistor is coupled to the first voltage signal terminal, and a second electrode of the seventh transistor is coupled to the first pull-down node. 
 
     
     
       5. The gate drive circuit according to  claim 2 , further comprising: an energy storage sub-circuit,
 wherein the energy storage sub-circuit is coupled to the pull-up node and the first output sub-circuit; and the energy storage sub-circuit is configured to store the voltage of the input signal transmitted to the pull-up node. 
 
     
     
       6. The gate drive circuit according to  claim 5 , wherein the first output sub-circuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the pull-up node, a first electrode of the eighth transistor is coupled to the clock signal terminal, and a second electrode of the eighth transistor is coupled to the first signal output terminal;
 the energy storage sub-circuit includes a first capacitor, a first terminal of the first capacitor is coupled to the pull-up node, and a second terminal of the first capacitor is coupled to the second electrode of the eighth transistor; 
 the second noise reduction sub-circuit includes a ninth transistor, a control electrode of the ninth transistor is coupled to the first pull-down node, a first electrode of the ninth transistor is coupled to the third voltage signal terminal, and a second electrode of the ninth transistor is coupled to the first signal output terminal; and 
 the reset sub-circuit includes a tenth transistor, a control electrode of the tenth transistor is coupled to the reset signal terminal, a first electrode of the tenth transistor is coupled to the first voltage signal terminal, and a second electrode of the tenth transistor is coupled to the pull-up node. 
 
     
     
       7. The gate drive circuit according to  claim 5 , further comprising:
 a second pull-down node, a second pull-down control sub-circuit, a third noise reduction sub-circuit and a second pull-down sub-circuit, wherein the second pull-down control sub-circuit is coupled to the first voltage signal terminal, a fourth voltage signal terminal, the pull-up node and the second pull-down node; 
 the second pull-down control sub-circuit is configured to transmit: a fourth voltage signal received at the fourth voltage signal terminal to the second pull-down node in response to the fourth voltage signal received at the fourth voltage signal terminal and the voltage of the first voltage signal transmitted to the pull-up node; and 
 transmit the first voltage signal received at the first voltage signal terminal to the second pull-down node in response to the fourth voltage signal received at the fourth voltage signal terminal and the voltage of the input signal transmitted to the pull-up node; 
 the third noise reduction sub-circuit is coupled to the pull-up node, the second pull-down node and the first voltage signal terminal; and 
 the third noise reduction sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the pull-up node under control of a voltage of the fourth voltage signal transmitted to the second pull-down node; 
 the second pull-down sub-circuit is coupled to the signal input terminal, the second pull-down node and the first voltage signal terminal; and 
 the second pull-down sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the second pull-down node in response to the input signal received at the signal input terminal, so that the third noise reduction sub-circuit is turned off under control of the voltage of the first voltage signal transmitted to the second pull-down node to stop transmitting the first voltage signal to the pull-up node. 
 
     
     
       8. The gate drive circuit according to  claim 7 , wherein the second pull-down control sub-circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second control node, wherein a control electrode of the eleventh transistor is coupled to the fourth voltage signal terminal, a first electrode of the eleventh transistor is coupled to the fourth voltage signal terminal, and a second electrode of the eleventh transistor is coupled to the second control node;
 a control electrode of the twelfth transistor is coupled to the pull-up node, a first electrode of the twelfth transistor is coupled to the first voltage signal terminal, and a second electrode of the twelfth transistor is coupled to the second control node; 
 a control electrode of the thirteenth transistor is coupled to the second control node, a first electrode of the thirteenth transistor is coupled to the fourth voltage signal terminal, and a second electrode of the thirteenth transistor is coupled to the second pull-down node; and 
 a control electrode of the fourteenth transistor is coupled to the pull-up node, a first electrode of the fourteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the fourteenth transistor is coupled to the second pull-down node; 
 the third noise reduction sub-circuit includes a fifteenth transistor, a control electrode of the fifteenth transistor is coupled to the second pull-down node, a first electrode of the fifteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifteenth transistor is coupled to the pull-up node; and 
 the second pull-down sub-circuit includes a sixteenth transistor, a control electrode of the sixteenth transistor is coupled to the signal input terminal, a first electrode of the sixteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the sixteenth transistor is coupled to the second pull-down node. 
 
     
     
       9. The gate drive circuit according to  claim 7 , further comprising a fourth noise reduction sub-circuit, wherein the fourth noise reduction sub-circuit is coupled to the second pull-down node, the third voltage signal terminal and the first signal output terminal;
 the fourth noise reduction sub-circuit is configured to transmit the third voltage signal received at the third voltage signal terminal to the first signal output terminal under the control of the voltage of the fourth voltage signal transmitted to the second pull-down node. 
 
     
     
       10. The gate drive circuit according to  claim 9 , wherein the fourth noise reduction sub-circuit includes a seventeenth transistor;
 a control electrode of the seventeenth transistor is coupled to the second pull-down node, a first electrode of the seventeenth transistor is coupled to the third voltage signal terminal, and a second electrode of the seventeenth transistor is coupled to the first signal output terminal. 
 
     
     
       11. The gate drive circuit according to  claim 9 , further comprising: a sixth noise reduction sub-circuit, wherein
 the sixth noise reduction sub-circuit is coupled to the second pull-down node, the first voltage signal terminal and the second signal output terminal; and
 the sixth noise reduction sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the second signal output terminal under the control of the voltage of the fourth voltage signal transmitted to the second pull-down node. 
 
 
     
     
       12. The gate drive circuit according to  claim 11 , wherein the second output sub-circuit includes an eighteenth transistor, a control electrode of the eighteenth transistor is coupled to the pull-up node, a first electrode of the eighteenth transistor is coupled to the clock signal terminal, and a second electrode of the eighteenth transistor is coupled to the second signal output terminal;
 the fifth noise reduction sub-circuit includes a nineteenth transistor, a control electrode of the nineteenth transistor is coupled to the first pull-down node, a first electrode of the nineteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the nineteenth transistor is coupled to the second signal output terminal; and 
 the sixth noise reduction sub-circuit includes a twentieth transistor, a control electrode of the twentieth transistor is coupled to the second pull-down node, a first electrode of the twentieth transistor is coupled to the first voltage signal terminal, and a second electrode of the twentieth transistor is coupled to the second signal output terminal. 
 
     
     
       13. The gate drive circuit according to  claim 2 , wherein the initialization sub-circuit includes a twenty-first transistor, a control electrode of the twenty-first transistor is coupled to the initialization signal terminal, a first electrode of the twenty-first transistor is coupled to the first voltage signal terminal, and a second electrode of the twenty-first transistor is coupled to the pull-up node. 
     
     
       14. The gate drive circuit according to  claim 2 , further comprising:
 a second pull-down node, an energy storage sub-circuit, a second pull-down control sub-circuit, a third noise reduction sub-circuit, a second pull-down sub-circuit, a fourth noise reduction sub-circuit, and a sixth noise reduction sub-circuit; 
 the first noise reduction sub-circuit includes a first transistor, the input sub-circuit includes a second transistor, the first pull-down sub-circuit includes a third transistor, and the first pull-down control sub-circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first control node; 
 the first output sub-circuit includes an eighth transistor, the energy storage sub-circuit includes a first capacitor, the second noise reduction sub-circuit includes a ninth transistor, and the reset sub-circuit includes a tenth transistor; 
 the second pull-down control sub-circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second control node, the third noise reduction sub-circuit includes a fifteenth transistor, the second pull-down sub-circuit includes a sixteenth transistor, and the fourth noise reduction sub-circuit includes a seventeenth transistor; 
 the second output sub-circuit includes an eighteenth transistor, the fifth noise reduction sub-circuit includes a nineteenth transistor, the sixth noise reduction sub-circuit includes a twentieth transistor, and the initialization sub-circuit includes a twenty-first transistor; 
 a control electrode of the first transistor is coupled to the first pull-down node, a first electrode of the first transistor is coupled to the first voltage signal terminal, and a second electrode of the first transistor is coupled to the pull-up node; 
 a control electrode of the second transistor is coupled to the signal input terminal, a first electrode of the second transistor is coupled to the signal input terminal, and a second electrode of the second transistor is coupled to the pull-up node; 
 a control electrode of the third transistor is coupled to the signal input terminal, a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the first pull-down node; 
 a control electrode of the fourth transistor is coupled to the second voltage signal terminal, a first electrode of the fourth transistor is coupled to the second voltage signal terminal, and a second electrode of the fourth transistor is coupled to the first control node; 
 a control electrode of the fifth transistor is coupled to the pull-up node, a first electrode of the fifth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifth transistor is coupled to the first control node; 
 a control electrode of the sixth transistor is coupled to the first control node, a first electrode of the sixth transistor is coupled to the second voltage signal terminal, and a second electrode of the sixth transistor is coupled to the first pull-down node; 
 a control electrode of the seventh transistor is coupled to the pull-up node, a first electrode of the seventh transistor is coupled to the first voltage signal terminal, and a second electrode of the seventh transistor is coupled to the first pull-down node; 
 a control electrode of the eighth transistor is coupled to the pull-up node, a first electrode of the eighth transistor is coupled to the clock signal terminal, and a second electrode of the eighth transistor is coupled to the first signal output terminal; 
 a first terminal of the first capacitor is coupled to the pull-up node, and a second terminal of the first capacitor is coupled to the second electrode of the eighth transistor; 
 a control electrode of the ninth transistor is coupled to the first pull-down node, a first electrode of the ninth transistor is coupled to a third voltage signal terminal, and a second electrode of the ninth transistor is coupled to the first signal output terminal; 
 a control electrode of the tenth transistor is coupled to the reset signal terminal, a first electrode of the tenth transistor is coupled to the first voltage signal terminal, and a second electrode of the tenth transistor is coupled to the pull-up node; 
 a control electrode of the eleventh transistor is coupled to a fourth voltage signal terminal, a first electrode of the eleventh transistor is coupled to the fourth voltage signal terminal, and a second electrode of the eleventh transistor is coupled to the second control node; 
 a control electrode of the twelfth transistor is coupled to the pull-up node, a first electrode of the twelfth transistor is coupled to the first voltage signal terminal, and a second electrode of the twelfth transistor is coupled to the second control node; 
 a control electrode of the thirteenth transistor is coupled to the second control node, a first electrode of the thirteenth transistor is coupled to the fourth voltage signal terminal, and a second electrode of the thirteenth transistor is coupled to the second pull-down node; 
 a control electrode of the fourteenth transistor is coupled to the pull-up node, a first electrode of the fourteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the fourteenth transistor is coupled to the second pull-down node; 
 a control electrode of the fifteenth transistor is coupled to the second pull-down node, a first electrode of the fifteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifteenth transistor is coupled to the pull-up node; 
 a control electrode of the sixteenth transistor is coupled to the signal input terminal, a first electrode of the sixteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the sixteenth transistor is coupled to the second pull-down node; 
 a control electrode of the seventeenth transistor is coupled to the second pull-down node, a first electrode of the seventeenth transistor is coupled to the third voltage signal terminal, and a second electrode of the seventeenth transistor is coupled to the first signal output terminal; 
 a control electrode of the eighteenth transistor is coupled to the pull-up node, a first electrode of the eighteenth transistor is coupled to the clock signal terminal, and a second electrode of the eighteenth transistor is coupled to the second signal output terminal; 
 a control electrode of the nineteenth transistor is coupled to the first pull-down node, a first electrode of the nineteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the nineteenth transistor is coupled to the second signal output terminal; 
 a control electrode of the twentieth transistor is coupled to the second pull-down node, a first electrode of the twentieth transistor is coupled to the first voltage signal terminal, and a second electrode of the twentieth transistor is coupled to the second signal output terminal; and 
 a control electrode of the twenty-first transistor is coupled to an initialization signal terminal, a first electrode of the twenty-first transistor is coupled to the first voltage signal terminal, and a second electrode of the twenty-first transistor is coupled to the pull-up node.