Hybrid virtual GPU co-scheduling

Abstract

An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.

We claim: 
     
       1. An electronic processing system, comprising:
 a general processor; 
 a graphics processor; 
 memory communicatively coupled to the general processor and the graphics processor; and 
 logic communicatively coupled to the general processor and the graphics processor to:
 manage one or more virtual graphic processor units, 
 map schedule information into a graphics memory space, wherein the schedule information includes schedule account information, 
 
 co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions, 
 co-schedule the one or more virtual graphic processor units based on the graphics processor instructions when a graphics processor schedule stub inserted at an end of a virtual graphics processor workload is reached, and 
 update the schedule account information in the graphics memory space based on one or more of graphics memory space access instructions and graphics processor pipeline instructions, wherein the schedule account information is associated with scheduling policies implemented by graphics processor commands. 
 
     
     
       2. The system of  claim 1 , wherein the logic is further to:
 share the schedule information in the graphics memory space between the general processor and the graphics processor. 
 
     
     
       3. The system of  claim 2 , wherein the schedule information includes workload queue information. 
     
     
       4. The system of  claim 2 , wherein the logic is further to:
 generate the virtual graphics processor workload to be a shadow virtual graphics processor workload; and 
 insert the graphics processor schedule stub at the end of the shadow virtual graphics processor workload. 
 
     
     
       5. The system of  claim 1 , wherein the logic is further to:
 co-schedule based on the general processor instruction after the graphics processor becomes idle. 
 
     
     
       6. A semiconductor package apparatus, comprising:
 one or more substrates; and 
 logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to: 
 manage one or more virtual graphic processor units, 
 map schedule information into a graphics memory space, wherein the schedule information includes schedule account information, 
 co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions, 
 co-schedule the one or more virtual graphic processor units based on the graphics processor instructions when a graphics processor schedule stub inserted at an end of a virtual graphics processor workload is reached and 
 update the schedule account information in the graphics memory space based on one or more of graphics memory space access instructions and graphics processor pipeline instructions, wherein the schedule account information is associated with scheduling policies implemented by graphics processor commands. 
 
     
     
       7. The apparatus of  claim 6 , wherein the logic is further to:
 share the schedule information in the graphics memory space between a general processor and a graphics processor. 
 
     
     
       8. The apparatus of  claim 7 , wherein the schedule information includes workload queue information. 
     
     
       9. The apparatus of  claim 7 , wherein the logic is further to:
 generate the virtual graphics processor workload to be a shadow virtual graphics processor workload; and 
 insert the graphics processor schedule stub at the end of the shadow virtual graphics processor workload. 
 
     
     
       10. The apparatus of  claim 6 , wherein the logic is further to:
 co-schedule based on the general processor instructions after a graphics processor becomes idle. 
 
     
     
       11. The apparatus of  claim 6 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. 
     
     
       12. A method of co-scheduling a virtual graphics processor, comprising:
 managing one or more virtual graphic processor units; 
 mapping schedule information into a graphics memory space, wherein the schedule information includes schedule account information; 
 co-scheduling the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions; 
 co-scheduling the one or more virtual graphic processor units based on the graphics processor instructions when a graphics processor schedule stub inserted at an end of a virtual graphics processor workload is reached; and 
 updating the schedule account information in the graphics memory space based on one or more of graphics memory space access instructions and graphics processor pipeline instructions, wherein the schedule account information is associated with scheduling policies implemented by graphics processor commands. 
 
     
     
       13. The method of  claim 12 , further comprising:
 sharing the schedule information in the graphics memory space between a general processor and a graphics processor. 
 
     
     
       14. The method of  claim 13 , wherein the schedule information includes workload queue information. 
     
     
       15. The method of  claim 13 , further comprising:
 generating the virtual graphics processor workload to be a shadow virtual graphics processor workload; and 
 inserting the graphics processor schedule stub at the end of the shadow virtual graphics processor workload. 
 
     
     
       16. The method of  claim 12 , further comprising:
 co-scheduling based on the general processor instructions after a graphics processor becomes idle. 
 
     
     
       17. At least one non-transitory computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
 manage one or more virtual graphic processor units; 
 map schedule information into a graphics memory space, wherein the schedule information includes schedule account information; 
 co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions; 
 co-schedule the one or more virtual graphic processor units based on the graphics processor instructions when a graphics processor schedule stub inserted at an end of a virtual graphics processor workload is reached; and 
 update the schedule account information in the graphics memory space based on one or more of graphics memory space access instructions and graphics processor pipeline instructions, wherein the schedule account information is associated with scheduling policies implemented by graphics processor commands. 
 
     
     
       18. The at least one non-transitory computer readable storage medium of  claim 17 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
 share the schedule information in the graphics memory space between a general processor and a graphics processor. 
 
     
     
       19. The at least one non-transitory computer readable storage medium of  claim 18 , wherein the schedule information includes workload queue information. 
     
     
       20. The at least one non-transitory computer readable storage medium of  claim 18 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
 generate the virtual graphics processor workload to be a shadow virtual graphics processor workload; and 
 insert the graphics processor schedule stub at the end of the shadow virtual graphics processor workload. 
 
     
     
       21. The at least one non-transitory computer readable storage medium of  claim 17 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
 co-schedule based on the general processor instructions after a graphics processor becomes idle.