Wiring board and semiconductor module including the same

Abstract

A wiring board may include a core portion having first and second surfaces, and first and second buildup portions on the first and second surfaces, respectively. Each of the first and second buildup portions may include a first insulating layer on the core portion, a wire pattern on the first insulating layer, a second insulating layer on the first insulating layer to cover the wire pattern, and a protection layer covering the second insulating layer and exposing a portion of the wire pattern. The second insulating layer may include a resin layer and inorganic fillers distributed in the resin layer. The fillers may not be provided in the protection layer, and the resin layer of the second insulating layer and the protection layer may be formed of the same material. The wire patterns of the first and second buildup portions may be electrically connected to each other.

What is claimed is: 
     
       1. A wiring board, comprising:
 a core portion having a first surface and a second surface, which are opposite to each other; and 
 a first buildup portion on the first surface and a second buildup portion on the second surface, respectively, 
 each of the first buildup portion and the second buildup portion including a first insulating layer on the core portion, a wire pattern on the first insulating layer, 
 a second insulating layer on the first insulating layer to cover the wire pattern, and 
 a protection layer covering the second insulating layer, 
 the protection layer exposing a portion of the wire pattern, 
 the second insulating layer including a resin layer and fillers, the fillers being distributed in the resin layer and being formed of an inorganic material, 
 the fillers not being in the protection layer, 
 the resin layer of the second insulating layer and the protection layer being formed of a same material 
 the wire pattern of the first buildup portion being electrically connected to the wire pattern of the second buildup portion, 
 a degree of roughness of a top surface of the protection layer is greater than a degree of roughness of the second insulating layer, and 
 the top surface of the protection layer faces away from the core portion. 
 
     
     
       2. The wiring board of  claim 1 , wherein the fillers comprise silicon oxide (SiO 2 ). 
     
     
       3. The wiring board of  claim 1 , wherein
 the first insulating layer comprises a prepreg (PPG), and 
 the resin layer and the protection layer comprise a solder resist. 
 
     
     
       4. The wiring board of  claim 1 , wherein the first buildup portion and the second buildup portion are symmetric to each other about the core portion. 
     
     
       5. The wiring board of  claim 1 , further comprising:
 an outer coupling terminal on a portion of the wire pattern of the second buildup portion that is exposed by the second insulating layer of the second buildup portion; and 
 a chip coupling pad on a portion of the wire pattern of the first buildup portion that is exposed by the second insulating layer of the first buildup portion. 
 
     
     
       6. A semiconductor module, comprising:
 a package substrate including, 
 a core portion, 
 a first upper insulating layer embedding an upper wire pattern on a top surface of the core portion, 
 upper fillers distributed in the first upper insulating layer, 
 an upper protection layer covering the first upper insulating layer, a material in the upper protection layer being a same material as in the first upper insulating layer, 
 a first lower insulating layer embedding a lower wire pattern on a bottom surface of the core portion, 
 lower fillers distributed in the first lower insulating layer, and 
 a lower protection layer covering the first lower insulating layer, 
 a material in the lower protection layer being a same material as in the first lower insulating layer, and
 a thickness of the upper protection layer and a thickness of the lower protection layer ranging from 1 μm to 3 μm; 
 
 a semiconductor chip on the package substrate; 
 a mold layer on the package substrate, the mold layer covering the semiconductor chip, the mold layer being spaced apart from the first upper insulating layer and the upper fillers by the upper protection layer; and 
 outer coupling terminals below the package substrate and connected to a lower surface of the package substrate, 
 wherein 
 a degree of roughness of a top surface of the upper protection layer is greater than a degree of roughness of a top surface of the first upper insulating layer, and 
 a degree of roughness of a bottom surface of the lower protection layer is greater than a degree of roughness of a bottom surface of the first lower insulating layer. 
 
     
     
       7. The semiconductor module of  claim 6 , further comprising:
 a connection terminal, wherein 
 the semiconductor chip is on the upper protection layer, 
 the upper protection layer exposes an exposed portion of the upper wire pattern, and 
 the semiconductor chip is coupled to the exposed portion of the upper wire pattern using the connection terminal. 
 
     
     
       8. The semiconductor module of  claim 6 , wherein
 the outer coupling terminals are on the lower protection layer, 
 the lower protection layer exposes an exposed portion of the lower wire pattern, and 
 each of the outer coupling terminals is on the exposed portion of the lower wire pattern. 
 
     
     
       9. The semiconductor module of  claim 6 , wherein
 the upper fillers are not provided in the upper protection layer, and 
 the lower fillers are not provided in the lower protection layer. 
 
     
     
       10. The semiconductor module of  claim 6 , wherein the upper fillers and the lower fillers comprise silicon oxide (SiO 2 ). 
     
     
       11. The semiconductor module of  claim 6 , wherein the first upper insulating layer, the first lower insulating layer, the upper protection layer, and the lower protection layer comprise a solder resist. 
     
     
       12. The semiconductor module of  claim 6 , further comprising:
 a second upper insulating layer between the core portion and the first upper insulating layer; and 
 a second lower insulating layer between the core portion and the first lower insulating layer. 
 
     
     
       13. The semiconductor module of  claim 12 , wherein
 the upper wire pattern is on a top surface of the second upper insulating layer, 
 the first upper insulating layer covers the upper wire pattern, on the top surface of the second upper insulating layer, 
 the lower wire pattern is on a bottom surface of the second lower insulating layer, 
 the first lower insulating layer covers the lower wire pattern, on the bottom surface of the second lower insulating layer, and 
 the upper wire pattern is electrically connected to the lower wire pattern. 
 
     
     
       14. The semiconductor module of  claim 12 , wherein the second upper insulating layer and the second lower insulating layer comprise a prepreg (PPG). 
     
     
       15. A wiring board, comprising:
 a core portion; and 
 buildup portions on opposite surfaces of the core portion, 
 each of the buildup portions including a first insulating layer on the core portion, a wire pattern on the first insulating layer, a second insulating layer on the first insulating layer to cover the wire pattern, fillers distributed in the second insulating layer, and a protection layer covering the second insulating layer, 
 the protection layer exposing a portion of the wire pattern, 
 the second insulating layer being formed of a material different from a material of the first insulating layer, 
 the protection layer being formed of a same material as the second insulating layer, 
 the wire patterns of the buildup portions being electrically connected to each other, 
 a thickness of the protection layer ranging from 1 μm to 3 μm, 
 a degree of roughness of a surface of the protection layer being greater than a degree of roughness of the second insulating layer, and 
 the surface of the protection layer facing the core portion. 
 
     
     
       16. The wiring board of  claim 15 , wherein
 the first insulating layer comprises a prepreg (PPG), and 
 the second insulating layer and the protection layer comprise a solder resist. 
 
     
     
       17. The wiring board of  claim 15 , wherein the fillers comprise silicon oxide (SiO 2 ). 
     
     
       18. The wiring board of  claim 1 , wherein a thickness of the protection layer ranges from 1 μm to 3 μm.