Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data-writing module, a driving module, and a compensation module. The data-writing module is configured to selectively provide a data signal for the driving module. The driving module includes a driving transistor and is configured to provide a driving current to the light-emitting element. The compensation module is configured to compensate a threshold voltage of the driving transistor. A source of the driving transistor includes a first source and a second source, and a drain of the driving transistor includes a first drain and a second drain. A third driving portion is arranged between the first source and the second source. A first driving portion is arranged between the second source and the first drain.

What is claimed is: 
     
       1. A display panel, comprising:
 a pixel circuit and a light-emitting element, wherein:
 the pixel circuit includes a data-writing module, a driving module, and a compensation module; 
 the data-writing module is configured to selectively provide a data signal for the driving module; 
 the driving module includes a driving transistor and is configured to provide a driving current to the light-emitting element; 
 the compensation module is configured to compensate a threshold voltage of the driving transistor; 
 a source of the driving transistor includes a first source and a second source, and a drain of the driving transistor includes a first drain and a second drain; 
 a third driving portion is arranged between the first source and the second source, a first driving portion is arranged between the second source and the first drain, and a second driving portion is arranged between the first drain and the second drain; and 
 the data writing module is connected to the second source, and the compensation module is connected between a gate and the first drain. 
 
 
     
     
       2. The display panel according to  claim 1 , wherein:
 a length of a channel region of the first driving portion is L 1 , a length of a channel region of the second driving portion is L 2 , and a length of a channel region of the third driving portion is L 3 ; 
 L 3 /(L 1 +L 2 )≥ΔVs 1   d   2 /(ΔVgd 2 +V 0 )−1 and 0≤V 0 ≤ΔVs 1   g ×½; or 
 L 2 /(L 1 +L 3 )≥ΔVs 1   d   2 /(ΔVs 1   g +V 0 )−1 and 0≤V 0 ≤ΔVgd 2 ×½; 
 wherein ΔVs 1   d   2 =|Vs 1 −Vd 2 |, ΔVs 1   g =|Vs 1 −Vg|, and ΔVgd 2 =|Vg−Vd 2 |, in a light-emitting stage of the light-emitting element, Vs 1  is a voltage of the first source of the driving transistor, Vd 2  is a voltage of the second drain of the driving transistor, and Vg is a voltage of the gate of the driving transistor. 
 
     
     
       3. The display panel according to  claim 2 , wherein:
 L 3 /(L 1 +L 2 )≥ΔVs 1   d   2 /(ΔVgd 2 +V 1 )−1; and 
 L 2 /(L 1 +L 3 )≥ΔVs 1   d   2 /(ΔVs 1   g +V 1 )−1, wherein 0≤V 1 ≤2V. 
 
     
     
       4. The display panel according to  claim 1 , wherein:
 a channel region of an active layer includes a first segment, a second segment, a first site between the first segment and the second segment, the first drain is connected to the first site, the first segment is located at the first driving portion, and the second segment is located at the second driving portion, wherein:
 the gate includes a first side surface, the first side surface being a side surface of the gate closest to the first site, wherein:
 at least a partial region of the first segment has a distance away from the first side surface of the gate greater than a distance between the first site and the first side surface; and/or 
 
 at least a partial region of the second segment has a distance away from the first side surface of the gate greater than the distance between the first site and the first side surface. 
 
 
     
     
       5. The display panel according to  claim 4 , wherein:
 the gate further includes a second side surface, the second side surface is connected to the first side surface, and the first side surface and the second side surface are two side surfaces of the gate closest to the first site, wherein:
 at least a partial region of the first segment has a distance away from the second side surface of the gate greater than a distance between the first site and the second side surface; and/or 
 at least a partial region of the second segment has a distance away from the second side surface of the gate greater than the distance between the first site and the second side surface. 
 
 
     
     
       6. The display panel according to  claim 4 , wherein:
 the first site does not overlap with the gate. 
 
     
     
       7. The display panel according to  claim 4 , wherein:
 a length of a channel region of the first driving portion is L 1 , and a length of a channel region of the second driving is L 2 ; and 
 an auxiliary channel region is arranged between the first site and the first drain, a length of the auxiliary channel region is L 0 , wherein 0≤L 0 ≤(L 1 +L 2 )/30. 
 
     
     
       8. The display panel according to  claim 1 , wherein:
 the driving transistor is a PMOS transistor or an NMOS transistor. 
 
     
     
       9. A display device comprising a display panel including:
 a pixel circuit and a light-emitting element, wherein:
 the pixel circuit includes a data-writing module, a driving module, and a compensation module; 
 the data-writing module is configured to selectively provide a data signal for the driving module; 
 the driving module includes a driving transistor and is configured to provide a driving current to the light-emitting element; 
 the compensation module is configured to compensate a threshold voltage of the driving transistor; 
 a source of the driving transistor includes a first source and a second source, and a drain of the driving transistor includes a first drain and a second drain; 
 a third driving portion is arranged between the first source and the second source, a first driving portion is arranged between the second source and the first drain, and a second driving portion is arranged between the first drain and the second drain; and 
 the data writing module is connected to the second source, and the compensation module is connected between a gate and the first drain. 
 
 
     
     
       10. The device according to  claim 9 , wherein:
 a length of a channel region of the first driving portion is L 1 , a length of a channel region of the second driving portion is L 2 , and a length of a channel region of the third driving portion is L 3 ; 
 L 3 /(L 1 +L 2 )≥ΔVs 1   d   2 /(ΔVgd 2 +V 0 )−1 and 0≤V 0 ≤ΔVs 1   g ×½; or 
 L 2 /(L 1 +L 3 )≥ΔVs 1   d   2 /(ΔVs 1   g +V 0 )−1 and 0≤V 0 ≤ΔVgd 2 ×½; 
 wherein ΔVs 1   d   2 =|Vs 1 −Vd 2 |, ΔVs 1   g =|Vs 1 −Vg|, and ΔVgd 2 =|Vg−Vd 2 |, in a light-emitting stage of the light-emitting element, Vs 1  is a voltage of the first source of the driving transistor, Vd 2  is a voltage of the second drain of the driving transistor, and Vg is a voltage of the gate of the driving transistor. 
 
     
     
       11. The device according to  claim 10 , wherein:
 L 3 /(L 1 +L 2 )≥ΔVs 1   d   2 /(ΔVgd 2 +V 1 )−1; and 
 L 2 /(L 1 +L 3 )≥ΔVs 1   d   2 /(ΔVs 1   g +V 1 )−1, wherein 0≤V 1 ≤2V. 
 
     
     
       12. The device according to  claim 9 , wherein:
 a channel region of an active layer includes a first segment, a second segment, a first site between the first segment and the second segment, the first drain is connected to the first site, the first segment is located at the first driving portion, and the second segment is located at the second driving portion, wherein:
 the gate includes a first side surface, the first side surface being a side surface of the gate closest to the first site, wherein:
 at least a partial region of the first segment has a distance away from the first side surface of the gate greater than a distance between the first site and the first side surface; and/or 
 
 at least a partial region of the second segment has a distance away from the first side surface of the gate greater than the distance between the first site and the first side surface. 
 
 
     
     
       13. The device according to  12 , wherein:
 the gate further includes a second side surface, the second side surface is connected to the first side surface, and the first side surface and the second side surface are two side surfaces of the gate closest to the first site, wherein:
 at least a partial region of the first segment has a distance away from the second side surface of the gate greater than a distance between the first site and the second side surface; and/or 
 at least a partial region of the second segment has a distance away from the second side surface of the gate greater than the distance between the first site and the second side surface. 
 
 
     
     
       14. The device according to  claim 12 , wherein:
 the first site does not overlap with the gate. 
 
     
     
       15. The device according to  claim 12 , wherein:
 a length of a channel region of the first driving portion is L 1 , and a length of a channel region of the second driving is L 2 ; and 
 an auxiliary channel region is arranged between the first site and the first drain, a length of the auxiliary channel region is L 0 , wherein 0≤L 0 ≤(L 1 +L 2 )/30. 
 
     
     
       16. The device according to  claim 9 , wherein:
 the driving transistor is a PMOS transistor or an NMOS transistor.