Using network traffic metadata to control a processor

Abstract

In one embodiment, a processor includes: a plurality of cores to execute instructions; a power controller to control power consumption of the plurality of cores, the power controller to receive network traffic metadata from a classifier and control the power consumption of at least one of the plurality of cores based at least in part on the network traffic metadata; and a hardware feedback circuit coupled to the plurality of cores, the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores based at least in part on the network traffic metadata. Other embodiments are described and claimed.

What is claimed is: 
     
       1. A processor comprising:
 a plurality of cores to execute instructions; 
 a power controller to control power consumption of the plurality of cores, wherein the power controller is to receive network traffic metadata from a classifier and control the power consumption of at least one of the plurality of cores based at least in part on the network traffic metadata; and 
 a hardware feedback circuit coupled to the plurality of cores, the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores based at least in part on the network traffic metadata. 
 
     
     
       2. The processor of  claim 1 , wherein the processor further comprises a memory controller to receive the network traffic metadata, the memory controller to control a configuration of a memory hierarchy based at least in part on the network traffic metadata. 
     
     
       3. The processor of  claim 2 , wherein the processor further comprises a sideband interconnect to send the network traffic metadata to the memory controller. 
     
     
       4. The processor of  claim 2 , wherein the memory controller is to allocate a system cache to store information of a first thread based at least in part on the network traffic metadata. 
     
     
       5. The processor of  claim 4 , wherein the memory controller is to direct data of a second thread to at least one of the plurality of cores and not to the system cache, based at least in part on the network traffic metadata. 
     
     
       6. The processor of  claim 1 , wherein the power controller is to receive the network traffic metadata from a network interface circuit (NIC), the NIC comprising the classifier, the classifier comprising a machine learning packet classifier. 
     
     
       7. The processor of  claim 6 , wherein the machine learning packet classifier is to:
 identify a first traffic class based on a first plurality of incoming packets; 
 identify a second traffic class based on a second plurality of incoming packets; and 
 provide the network traffic metadata comprising an identification of the first traffic class and the second traffic class to a scheduler. 
 
     
     
       8. The processor of  claim 7 , wherein the hardware feedback circuit is to provide to the scheduler the hardware feedback information comprising a first energy efficiency capability and a first performance capability of a first core, the scheduler to schedule one or more first threads of the first traffic class to the first core based at least in part on the first energy efficiency capability, the first performance capability of the first core, and the identification of the first traffic class. 
     
     
       9. The processor of  claim 8 , wherein the scheduler is to schedule a network bound workload to the first core, the first core comprising an efficiency core, the scheduler to identify the network bound workload based at least in part on the network traffic metadata. 
     
     
       10. The processor of  claim 7 , wherein the machine learning packet classifier is further to provide the network traffic metadata comprising the identification of the first traffic class and the second traffic class to the power controller, wherein the power controller is to cause a reduction in acoustic noise of a thermal solution based at least in part on the identification of one or more of the first traffic class or the second class, and wherein the scheduler is to schedule at least one of the first traffic class or the second traffic class to at least one core of a performance core type to increase user responsiveness. 
     
     
       11. The processor of  claim 1 , wherein the power controller is to park at least one core of a first core type and control a frequency of at least one core of a second core type based at least in part on the network traffic metadata, and a scheduler is to schedule a first thread to the at least one core of the second core type, the first thread comprising a file transfer workload, the first core type comprising a performance core type and the second core type comprising an efficiency core type. 
     
     
       12. At least one computer readable medium comprising instructions, which when executed by a processor, cause the processor to execute a method comprising:
 receiving, from a classifier, network traffic metadata regarding incoming traffic to a system comprising the processor, the network traffic metadata comprising an indication of a type of the incoming traffic; and 
 controlling operation of the processor based at least in part on the network traffic metadata, comprising:
 providing first hint information from a hardware feedback circuit of the processor to a scheduler based at least in part on the network traffic metadata, the scheduler, based at least in part on the first hint information and the network traffic metadata, to schedule threads to one or more first cores of a first core type and one or more second cores of a second core type; and 
 controlling a frequency of at least the one or more first cores of the first core type, based at least in part on the network traffic metadata. 
 
 
     
     
       13. The at least one computer readable medium of  claim 12 , wherein the method further comprises:
 providing the network traffic metadata to a memory controller of the system; and 
 controlling, via the memory controller, operation of a memory of the system based at least in part on the network traffic metadata. 
 
     
     
       14. The at least one computer readable medium of  claim 13 , wherein controlling the operation of the memory comprises:
 allocating a system cache to store information of a first thread based at least in part on the network traffic metadata; and 
 directing information of a second thread to the processor and not to the system cache. 
 
     
     
       15. The at least one computer readable medium of  claim 12 , wherein the method further comprises:
 receiving the network traffic metadata in the hardware feedback circuit; 
 updating at least a portion of hardware feedback information based on the network traffic metadata; and 
 providing the updated hardware feedback information to the scheduler. 
 
     
     
       16. The at least one computer readable medium of  claim 12 , wherein controlling the operation of the processor based at least in part on the network traffic metadata comprises:
 parking at least one of the one or more first cores of the first core type; and 
 scheduling at least one thread to at least one of the one or more second cores of the second core type, the at least one thread comprising a non-real time workload, the first core type comprising a performant core type and the second core type comprising an efficient core type. 
 
     
     
       17. The at least one computer readable medium of  claim 12 , wherein the method further comprises receiving the network traffic metadata via a sideband interconnect coupled between the processor and a wireless communication circuit comprising the classifier to identify the type of incoming traffic. 
     
     
       18. A system comprising:
 a processor comprising:
 a first plurality of cores to execute instructions; 
 a second plurality of cores to execute instructions, the second plurality of cores heterogenous to the first plurality of cores; 
 a power controller to control, based at least in part on network traffic metadata, power consumption of the first plurality of cores and the second plurality of cores; and 
 a hardware feedback circuit coupled to at least the second plurality of cores, the hardware feedback circuit to provide, based at least in part on the network traffic metadata, hint information to a scheduler to cause the scheduler to schedule a workload on one or more of the second plurality of cores, the second plurality of cores having lower power consumption than the first plurality of cores; 
 a memory hierarchy coupled to the processor, the memory hierarchy comprising a system memory and a system cache coupled to the system memory; and 
 a memory controller coupled to the memory hierarchy, the memory controller to control, based at least in part on the network traffic metadata, a configuration of the memory hierarchy. 
 
 
     
     
       19. The system of  claim 18 , further comprising a network interface circuit coupled to the processor, the network interface circuit comprising a classifier to determine the network traffic metadata based on a plurality of packets communicated through the network interface circuit. 
     
     
       20. The system of  claim 19 , wherein the network interface circuit is to send the network traffic metadata to the processor via a sideband interconnect.