Hardware secure element, related processing system, integrated circuit, and device

Abstract

A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

What is claimed is: 
     
       1. An electronic circuit comprising:
 a first input terminal configured to receive a command field; 
 a first output terminal configured to deliver a service handler address indicative of a start address of a service handler of a set of service handlers; and 
 a message handler circuit coupled between the first input terminal and the first output terminal, the message handler circuit configured to:
 receive a handler number indicative of a number of service handlers in the set of service handlers, 
 receive a look-up-table (LUT) start address indicative of a start address of a LUT, 
 receive a first error signal indicative of whether there is an error associated with the command field, 
 determine the service handler address based on the handler number, the LUT start address, and the first error signal, and 
 deliver the service handler address to the first output terminal. 
 
 
     
     
       2. The electronic circuit of  claim 1 , wherein the message handler circuit comprises a first multiplexer comprising:
 an output coupled to the first output terminal; 
 a first selection input configured to receive the first error signal; 
 a first data input configured to receive first data, the first data being based on the command field and the LUT start address; and 
 a second data input configured to receive second data, wherein the first multiplexer is configured to couple the second data input of the first multiplexer to the output of the first multiplexer when the first error signal indicates that there is an error associated with the command field. 
 
     
     
       3. The electronic circuit of  claim 2 , wherein the message handler circuit further comprises a digital comparator having a first input configured to receive the command field, and a second input configured to receive the handler number, wherein the first multiplexer further comprises:
 a second selection input coupled to an output of the digital comparator; and 
 a third data input configured to receive third data, wherein the first multiplexer is configured to couple the first data input of the first multiplexer to the output of the first multiplexer when the command field is lower than the handler number and the first error signal indicates that there are no errors associated with the command field, and wherein the first multiplexer is configured to couple the third data input of the first multiplexer to the output of the first multiplexer when the command field is higher than the handler number and the first error signal indicates that there are no errors associated with the command field. 
 
     
     
       4. The electronic circuit of  claim 3 , wherein the message handler circuit further comprises:
 a first multiplier having a first input configured to receive a first factor and a second input coupled to the first input terminal, the first factor being a positive integer; and 
 a first adder having a first input configured to receive the LUT start address, a second input coupled to an output of the first multiplier, and an output coupled to the first data input of the first multiplexer. 
 
     
     
       5. The electronic circuit of  claim 4 , wherein the message handler circuit further comprises a second adder having an input coupled to the first input terminal, a second input configured to receive an offset, and an output coupled to the second data input of the first multiplier. 
     
     
       6. The electronic circuit of  claim 2 , wherein the message handler circuit further comprises a second multiplexer having a selection input configured to receive an error type signal, a first input configured to receive a first factor, the first factor being a positive integer, a second input configured to receive the first factor multiplied by two, and an output coupled to the second data input of the first multiplexer. 
     
     
       7. The electronic circuit of  claim 6 , wherein the message handler circuit further comprises a first adder having a first input coupled to the output of the second multiplexer, a second input configured to receive the LUT start address, and an output coupled to the second data input of the first multiplexer. 
     
     
       8. The electronic circuit of  claim 1 , further comprising a memory configured to store the LUT and the set of service handlers. 
     
     
       9. The electronic circuit of  claim 1 , wherein the first input terminal is coupled to a non-secured processing unit, and wherein the first output terminal is coupled to a secure processing unit. 
     
     
       10. The electronic circuit of  claim 1 , further comprising a first register configured to store the handler number. 
     
     
       11. The electronic circuit of  claim 1 , further comprising a first register configured to store the LUT start address. 
     
     
       12. The electronic circuit of  claim 1 , further comprising:
 a second input terminal configured to receive a parameter field; and 
 a parameter check circuit configured to generate a second error signal indicative of whether the parameter field is valid, wherein the first error signal is based on the second error signal. 
 
     
     
       13. The electronic circuit of  claim 12 , wherein the parameter check circuit comprises:
 an OR gate having an output configured to generate the second error signal; and 
 a plurality of parameter check sub-circuits having respective outputs coupled to respective inputs of the OR gate. 
 
     
     
       14. An electronic circuit comprising:
 a first input terminal configured to receive a command field; 
 a second input terminal configured to receive a parameter field; 
 a first output terminal configured to deliver a service handler address indicative of a start address of a service handler of a set of service handlers; 
 a parameter check circuit configured to generate a first error signal indicative of whether the parameter field is valid; and 
 a message handler circuit configured to:
 receive a handler number indicative of a number of service handlers in the set of service handlers, 
 receive a look-up-table (LUT) start address indicative of a start address of a LUT, 
 receive a second error signal indicative of whether there is an error associated with the command field, wherein the second error signal is based on the first error signal, 
 determine the service handler address based on the handler number, the LUT start address, and the second error signal, and 
 deliver the service handler address to the first output terminal. 
 
 
     
     
       15. The electronic circuit of  claim 14 , wherein the message handler circuit comprises a first multiplexer comprising:
 an output coupled to the first output terminal; 
 a first selection input configured to receive the second error signal; 
 a first data input configured to receive first data, the first data being based on the command field and the LUT start address; and 
 a second data input configured to receive second data, wherein the first multiplexer is configured to couple the second data input of the first multiplexer to the output of the first multiplexer when the second error signal indicates that there is an error associated with the command field. 
 
     
     
       16. The electronic circuit of  claim 15 , further comprising a third input terminal configured to receive a transmission error signal, wherein the second error signal is further based on the transmission error signal. 
     
     
       17. The electronic circuit of  claim 16 , wherein the message handler circuit further comprises a second multiplexer comprising:
 a selection input configured to receive an error type signal that is based on the transmission error signal and on the first error signal; 
 a first input configured to receive a first factor, the first factor being a positive integer; 
 a second input configured to receive the first factor multiplied by two; and 
 an output coupled to the second data input of the first multiplexer. 
 
     
     
       18. An electronic circuit comprising:
 a digital comparator having a first input configured to receive a command field, and a second input configured to receive a handler number indicative of a number of service handlers in a set of service handlers; and 
 a first multiplexer comprising:
 an output configured to deliver a service handler address indicative of a start address of a service handler of the set of service handlers, 
 a first selection input configured to receive a first error signal, wherein the first error signal is indicative of whether there is an error associated with the command field, 
 a second selection input coupled to an output of the digital comparator, 
 a first data input configured to receive first data, the first data being based on the command field and on a look-up-table (LUT) start address, wherein the LUT start address is indicative of a start address of a LUT, 
 a second data input configured to receive second data, the second data being based on the LUT start address, and 
 a third data input configured to receive third data, wherein the first multiplexer is configured to:
 couple the third data input of the first multiplexer to the output of the first multiplexer when the first error signal indicates that there is an error associated with the command field, 
 couple the first data input of the first multiplexer to the output of the first multiplexer when the command field is lower than the handler number and the first error signal indicates that there are no errors associated with the command field, and 
 couple the second data input of the first multiplexer to the output of the first multiplexer when the command field is higher than the handler number and the first error signal indicates that there are no errors associated with the command field. 
 
 
 
     
     
       19. The electronic circuit of  claim 18 , further comprising:
 a first multiplier having a first input configured to receive a first factor and a second input coupled to the first input of the digital comparator, the first factor being a positive integer; and 
 a first adder having a first input configured to receive the LUT start address, a second input coupled to an output of the first multiplier, and an output coupled to the first data input of the first multiplexer. 
 
     
     
       20. The electronic circuit of  claim 19 , wherein the second data input of the first multiplexer is configured to receive the LUT start address.